Clang-tidy fixes

1 files changed, 58 insertions, 74 deletions

diff --git a/include/arch/x86_64/linux/mdio.h b/include/arch/x86_64/linux/mdio.h
index a05b1eac..b802fbe8 100644
--- a/include/arch/x86_64/linux/mdio.h
+++ b/include/arch/x86_64/linux/mdio.h
@@ -60,37 +60,33 @@
 /* Media-dependent registers. */
 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
 #define MDIO_PMA_10GBT_TXPWR   131 /* 10GBASE-T TX power control */
-#define MDIO_PMA_10GBT_SNR                   \
-	133 /* 10GBASE-T SNR margin, lane A. \
-	     * Lanes B-D are numbered 134-136. */
-#define MDIO_PMA_10GBR_FSRT_CSR \
-	147 /* 10GBASE-R fast retrain status and control */
-#define MDIO_PMA_10GBR_FECABLE 170  /* 10GBASE-R FEC ability */
-#define MDIO_PCS_10GBX_STAT1   24   /* 10GBASE-X PCS status 1 */
-#define MDIO_PCS_10GBRT_STAT1  32   /* 10GBASE-R/-T PCS status 1 */
-#define MDIO_PCS_10GBRT_STAT2  33   /* 10GBASE-R/-T PCS status 2 */
-#define MDIO_AN_10GBT_CTRL     32   /* 10GBASE-T auto-negotiation control */
-#define MDIO_AN_10GBT_STAT     33   /* 10GBASE-T auto-negotiation status */
-#define MDIO_B10L_PMA_CTRL     2294 /* 10BASE-T1L PMA control */
-#define MDIO_PMA_10T1L_STAT    2295 /* 10BASE-T1L PMA status */
-#define MDIO_PCS_10T1L_CTRL    2278 /* 10BASE-T1L PCS control */
-#define MDIO_PMA_PMD_BT1       18   /* BASE-T1 PMA/PMD extended ability */
-#define MDIO_AN_T1_CTRL	       512  /* BASE-T1 AN control */
-#define MDIO_AN_T1_STAT	       513  /* BASE-T1 AN status */
-#define MDIO_AN_T1_ADV_L       514 /* BASE-T1 AN advertisement register [15:0] */
-#define MDIO_AN_T1_ADV_M       515 /* BASE-T1 AN advertisement register [31:16] */
-#define MDIO_AN_T1_ADV_H       516 /* BASE-T1 AN advertisement register [47:32] */
-#define MDIO_AN_T1_LP_L \
-	517 /* BASE-T1 AN LP Base Page ability register [15:0] */
-#define MDIO_AN_T1_LP_M \
-	518 /* BASE-T1 AN LP Base Page ability register [31:16] */
-#define MDIO_AN_T1_LP_H \
-	519 /* BASE-T1 AN LP Base Page ability register [47:32] */
-#define MDIO_AN_10BT1_AN_CTRL 526  /* 10BASE-T1 AN control register */
-#define MDIO_AN_10BT1_AN_STAT 527  /* 10BASE-T1 AN status register */
-#define MDIO_PMA_PMD_BT1_CTRL 2100 /* BASE-T1 PMA/PMD control register */
-#define MDIO_PCS_1000BT1_CTRL 2304 /* 1000BASE-T1 PCS control register */
-#define MDIO_PCS_1000BT1_STAT 2305 /* 1000BASE-T1 PCS status register */
+#define MDIO_PMA_10GBT_SNR                                            \
+	133			     /* 10GBASE-T SNR margin, lane A. \
+				      * Lanes B-D are numbered 134-136. */
+#define MDIO_PMA_10GBR_FSRT_CSR 147  /* 10GBASE-R fast retrain status and control */
+#define MDIO_PMA_10GBR_FECABLE	170  /* 10GBASE-R FEC ability */
+#define MDIO_PCS_10GBX_STAT1	24   /* 10GBASE-X PCS status 1 */
+#define MDIO_PCS_10GBRT_STAT1	32   /* 10GBASE-R/-T PCS status 1 */
+#define MDIO_PCS_10GBRT_STAT2	33   /* 10GBASE-R/-T PCS status 2 */
+#define MDIO_AN_10GBT_CTRL	32   /* 10GBASE-T auto-negotiation control */
+#define MDIO_AN_10GBT_STAT	33   /* 10GBASE-T auto-negotiation status */
+#define MDIO_B10L_PMA_CTRL	2294 /* 10BASE-T1L PMA control */
+#define MDIO_PMA_10T1L_STAT	2295 /* 10BASE-T1L PMA status */
+#define MDIO_PCS_10T1L_CTRL	2278 /* 10BASE-T1L PCS control */
+#define MDIO_PMA_PMD_BT1	18   /* BASE-T1 PMA/PMD extended ability */
+#define MDIO_AN_T1_CTRL		512  /* BASE-T1 AN control */
+#define MDIO_AN_T1_STAT		513  /* BASE-T1 AN status */
+#define MDIO_AN_T1_ADV_L	514  /* BASE-T1 AN advertisement register [15:0] */
+#define MDIO_AN_T1_ADV_M	515  /* BASE-T1 AN advertisement register [31:16] */
+#define MDIO_AN_T1_ADV_H	516  /* BASE-T1 AN advertisement register [47:32] */
+#define MDIO_AN_T1_LP_L		517  /* BASE-T1 AN LP Base Page ability register [15:0] */
+#define MDIO_AN_T1_LP_M		518  /* BASE-T1 AN LP Base Page ability register [31:16] */
+#define MDIO_AN_T1_LP_H		519  /* BASE-T1 AN LP Base Page ability register [47:32] */
+#define MDIO_AN_10BT1_AN_CTRL	526  /* 10BASE-T1 AN control register */
+#define MDIO_AN_10BT1_AN_STAT	527  /* 10BASE-T1 AN status register */
+#define MDIO_PMA_PMD_BT1_CTRL	2100 /* BASE-T1 PMA/PMD control register */
+#define MDIO_PCS_1000BT1_CTRL	2304 /* 1000BASE-T1 PCS control register */
+#define MDIO_PCS_1000BT1_STAT	2305 /* 1000BASE-T1 PCS status register */
 
 /* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
 #define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
@@ -305,11 +301,10 @@
 #define MDIO_PCS_10GBRT_STAT2_BER 0x3f00
 
 /* AN 10GBASE-T control register. */
-#define MDIO_AN_10GBT_CTRL_ADVFSRT2_5G \
-	0x0020 /* Advertise 2.5GBASE-T fast retrain */
-#define MDIO_AN_10GBT_CTRL_ADV2_5G 0x0080 /* Advertise 2.5GBASE-T */
-#define MDIO_AN_10GBT_CTRL_ADV5G   0x0100 /* Advertise 5GBASE-T */
-#define MDIO_AN_10GBT_CTRL_ADV10G  0x1000 /* Advertise 10GBASE-T */
+#define MDIO_AN_10GBT_CTRL_ADVFSRT2_5G 0x0020 /* Advertise 2.5GBASE-T fast retrain */
+#define MDIO_AN_10GBT_CTRL_ADV2_5G     0x0080 /* Advertise 2.5GBASE-T */
+#define MDIO_AN_10GBT_CTRL_ADV5G       0x0100 /* Advertise 5GBASE-T */
+#define MDIO_AN_10GBT_CTRL_ADV10G      0x1000 /* Advertise 10GBASE-T */
 
 /* AN 10GBASE-T status register. */
 #define MDIO_AN_10GBT_STAT_LP2_5G   0x0020 /* LP is 2.5GBT capable */
@@ -331,16 +326,14 @@
 #define MDIO_PMA_10T1L_CTRL_PMA_RST   0x8000 /* MA reset */
 
 /* 10BASE-T1L PMA status register. */
-#define MDIO_PMA_10T1L_STAT_LINK     0x0001 /* PMA receive link up */
-#define MDIO_PMA_10T1L_STAT_FAULT    0x0002 /* Fault condition detected */
-#define MDIO_PMA_10T1L_STAT_POLARITY 0x0004 /* Receive polarity is reversed */
-#define MDIO_PMA_10T1L_STAT_RECV_FAULT \
-	0x0200 /* Able to detect fault on receive path */
-#define MDIO_PMA_10T1L_STAT_EEE	      0x0400 /* PHY has EEE ability */
-#define MDIO_PMA_10T1L_STAT_LOW_POWER 0x0800 /* PMA has low-power ability */
-#define MDIO_PMA_10T1L_STAT_2V4_ABLE \
-	0x1000 /* PHY has 2.4 Vpp operating mode ability */
-#define MDIO_PMA_10T1L_STAT_LB_ABLE 0x2000 /* PHY has loopback ability */
+#define MDIO_PMA_10T1L_STAT_LINK       0x0001 /* PMA receive link up */
+#define MDIO_PMA_10T1L_STAT_FAULT      0x0002 /* Fault condition detected */
+#define MDIO_PMA_10T1L_STAT_POLARITY   0x0004 /* Receive polarity is reversed */
+#define MDIO_PMA_10T1L_STAT_RECV_FAULT 0x0200 /* Able to detect fault on receive path */
+#define MDIO_PMA_10T1L_STAT_EEE	       0x0400 /* PHY has EEE ability */
+#define MDIO_PMA_10T1L_STAT_LOW_POWER  0x0800 /* PMA has low-power ability */
+#define MDIO_PMA_10T1L_STAT_2V4_ABLE   0x1000 /* PHY has 2.4 Vpp operating mode ability */
+#define MDIO_PMA_10T1L_STAT_LB_ABLE    0x2000 /* PHY has loopback ability */
 
 /* 10BASE-T1L PCS control register. */
 #define MDIO_PCS_10T1L_CTRL_LB	  0x4000 /* Enable PCS level loopback mode */
@@ -362,24 +355,21 @@
 #define MDIO_AN_T1_ADV_L_NEXT_PAGE_REQ ADVERTISE_NPAGE
 
 /* BASE-T1 auto-negotiation advertisement register [31:16] */
-#define MDIO_AN_T1_ADV_M_B10L                          \
-	0x4000 /* device is compatible with 10BASE-T1L \
-		*/
+#define MDIO_AN_T1_ADV_M_B10L                                                   \
+	0x4000				/* device is compatible with 10BASE-T1L \
+					 */
 #define MDIO_AN_T1_ADV_M_1000BT1 0x0080 /* advertise 1000BASE-T1 */
 #define MDIO_AN_T1_ADV_M_100BT1	 0x0020 /* advertise 100BASE-T1 */
 #define MDIO_AN_T1_ADV_M_MST	 0x0010 /* advertise master preference */
 
 /* BASE-T1 auto-negotiation advertisement register [47:32] */
-#define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ \
-	0x1000 /* 10BASE-T1L High Level Transmit Request */
-#define MDIO_AN_T1_ADV_H_10L_TX_HI \
-	0x2000 /* 10BASE-T1L High Level Transmit Ability */
+#define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level Transmit Request */
+#define MDIO_AN_T1_ADV_H_10L_TX_HI     0x2000 /* 10BASE-T1L High Level Transmit Ability */
 
 /* BASE-T1 AN LP Base Page ability register [15:0] */
-#define MDIO_AN_T1_LP_L_PAUSE_CAP  LPA_PAUSE_CAP
-#define MDIO_AN_T1_LP_L_PAUSE_ASYM LPA_PAUSE_ASYM
-#define MDIO_AN_T1_LP_L_FORCE_MS \
-	0x1000 /* LP Force Master/slave Configuration */
+#define MDIO_AN_T1_LP_L_PAUSE_CAP     LPA_PAUSE_CAP
+#define MDIO_AN_T1_LP_L_PAUSE_ASYM    LPA_PAUSE_ASYM
+#define MDIO_AN_T1_LP_L_FORCE_MS      0x1000 /* LP Force Master/slave Configuration */
 #define MDIO_AN_T1_LP_L_REMOTE_FAULT  LPA_RFAULT
 #define MDIO_AN_T1_LP_L_ACK	      LPA_LPACK
 #define MDIO_AN_T1_LP_L_NEXT_PAGE_REQ LPA_NPAGE
@@ -389,18 +379,14 @@
 #define MDIO_AN_T1_LP_M_B10L 0x4000 /* LP is compatible with 10BASE-T1L */
 
 /* BASE-T1 AN LP Base Page ability register [47:32] */
-#define MDIO_AN_T1_LP_H_10L_TX_HI_REQ \
-	0x1000 /* 10BASE-T1L High Level LP Transmit Request */
-#define MDIO_AN_T1_LP_H_10L_TX_HI \
-	0x2000 /* 10BASE-T1L High Level LP Transmit Ability */
+#define MDIO_AN_T1_LP_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level LP Transmit Request */
+#define MDIO_AN_T1_LP_H_10L_TX_HI     0x2000 /* 10BASE-T1L High Level LP Transmit Ability */
 
 /* 10BASE-T1 AN control register */
-#define MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L \
-	0x4000 /* 10BASE-T1L EEE ability advertisement */
+#define MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L 0x4000 /* 10BASE-T1L EEE ability advertisement */
 
 /* 10BASE-T1 AN status register */
-#define MDIO_AN_10BT1_AN_STAT_LPA_EEE_T1L \
-	0x4000 /* 10BASE-T1L LP EEE ability advertisement */
+#define MDIO_AN_10BT1_AN_STAT_LPA_EEE_T1L 0x4000 /* 10BASE-T1L LP EEE ability advertisement */
 
 /* BASE-T1 PMA/PMD control register */
 #define MDIO_PMA_PMD_BT1_CTRL_STRAP	  0x000F /* Type selection (Strap) */
@@ -408,10 +394,9 @@
 #define MDIO_PMA_PMD_BT1_CTRL_CFG_MST	  0x4000 /* MASTER-SLAVE config value */
 
 /* 1000BASE-T1 PCS control register */
-#define MDIO_PCS_1000BT1_CTRL_LOW_POWER 0x0800 /* Low power mode */
-#define MDIO_PCS_1000BT1_CTRL_DISABLE_TX \
-	0x4000				   /* Global PMA transmit disable */
-#define MDIO_PCS_1000BT1_CTRL_RESET 0x8000 /* Software reset value */
+#define MDIO_PCS_1000BT1_CTRL_LOW_POWER	 0x0800 /* Low power mode */
+#define MDIO_PCS_1000BT1_CTRL_DISABLE_TX 0x4000 /* Global PMA transmit disable */
+#define MDIO_PCS_1000BT1_CTRL_RESET	 0x8000 /* Software reset value */
 
 /* 1000BASE-T1 PCS status register */
 #define MDIO_PCS_1000BT1_STAT_LINK  0x0004 /* PCS Link is up */
@@ -473,11 +458,10 @@
 
 /* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */
 
-#define MDIO_PHY_ID_C45	  0x8000
-#define MDIO_PHY_ID_PRTAD 0x03e0
-#define MDIO_PHY_ID_DEVAD 0x001f
-#define MDIO_PHY_ID_C45_MASK \
-	(MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD)
+#define MDIO_PHY_ID_C45	     0x8000
+#define MDIO_PHY_ID_PRTAD    0x03e0
+#define MDIO_PHY_ID_DEVAD    0x001f
+#define MDIO_PHY_ID_C45_MASK (MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD)
 
 static __inline__ __u16 mdio_phy_id_c45(int prtad, int devad)
 {