Clang-tidy fixes

1 files changed, 31 insertions, 37 deletions

diff --git a/include/arch/x86_64/linux/serial_reg.h b/include/arch/x86_64/linux/serial_reg.h
index 981d703b..74188a3e 100644
--- a/include/arch/x86_64/linux/serial_reg.h
+++ b/include/arch/x86_64/linux/serial_reg.h
@@ -41,12 +41,11 @@
 
 #define UART_IIR_BUSY 0x07 /* DesignWare APB Busy Detect */
 
-#define UART_IIR_RX_TIMEOUT  0x0c /* OMAP RX Timeout interrupt */
-#define UART_IIR_XOFF	     0x10 /* OMAP XOFF/Special Character */
-#define UART_IIR_CTS_RTS_DSR 0x20 /* OMAP CTS/RTS/DSR Change */
-#define UART_IIR_64BYTE_FIFO 0x20 /* 16750 64 bytes FIFO */
-#define UART_IIR_FIFO_ENABLED \
-	0xc0 /* FIFOs enabled / port type identification */
+#define UART_IIR_RX_TIMEOUT	     0x0c /* OMAP RX Timeout interrupt */
+#define UART_IIR_XOFF		     0x10 /* OMAP XOFF/Special Character */
+#define UART_IIR_CTS_RTS_DSR	     0x20 /* OMAP CTS/RTS/DSR Change */
+#define UART_IIR_64BYTE_FIFO	     0x20 /* 16750 64 bytes FIFO */
+#define UART_IIR_FIFO_ENABLED	     0xc0 /* FIFOs enabled / port type identification */
 #define UART_IIR_FIFO_ENABLED_8250   0x00 /* 8250: no FIFO */
 #define UART_IIR_FIFO_ENABLED_16550  0x80 /* 16550: (broken/unusable) FIFO */
 #define UART_IIR_FIFO_ENABLED_16550A 0xc0 /* 16550A: FIFO enabled */
@@ -99,9 +98,8 @@
 	0x20 /* Go into 64 byte mode (TI16C750 and \
 		some Freescale UARTs) */
 
-#define UART_FCR_R_TRIG_SHIFT 6
-#define UART_FCR_R_TRIG_BITS(x) \
-	(((x) & UART_FCR_TRIGGER_MASK) >> UART_FCR_R_TRIG_SHIFT)
+#define UART_FCR_R_TRIG_SHIFT	  6
+#define UART_FCR_R_TRIG_BITS(x)	  (((x) & UART_FCR_TRIGGER_MASK) >> UART_FCR_R_TRIG_SHIFT)
 #define UART_FCR_R_TRIG_MAX_STATE 4
 
 #define UART_LCR 3 /* Out: Line Control Register */
@@ -138,29 +136,27 @@
 #define UART_MCR_RTS	0x02 /* RTS complement */
 #define UART_MCR_DTR	0x01 /* DTR complement */
 
-#define UART_LSR       5    /* In:  Line Status Register */
-#define UART_LSR_FIFOE 0x80 /* Fifo error */
-#define UART_LSR_TEMT  0x40 /* Transmitter empty */
-#define UART_LSR_THRE  0x20 /* Transmit-hold-register empty */
-#define UART_LSR_BI    0x10 /* Break interrupt indicator */
-#define UART_LSR_FE    0x08 /* Frame error indicator */
-#define UART_LSR_PE    0x04 /* Parity error indicator */
-#define UART_LSR_OE    0x02 /* Overrun error indicator */
-#define UART_LSR_DR    0x01 /* Receiver data ready */
-#define UART_LSR_BRK_ERROR_BITS \
-	(UART_LSR_BI | UART_LSR_FE | UART_LSR_PE | UART_LSR_OE)
-
-#define UART_MSR      6	   /* In:  Modem Status Register */
-#define UART_MSR_DCD  0x80 /* Data Carrier Detect */
-#define UART_MSR_RI   0x40 /* Ring Indicator */
-#define UART_MSR_DSR  0x20 /* Data Set Ready */
-#define UART_MSR_CTS  0x10 /* Clear to Send */
-#define UART_MSR_DDCD 0x08 /* Delta DCD */
-#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
-#define UART_MSR_DDSR 0x02 /* Delta DSR */
-#define UART_MSR_DCTS 0x01 /* Delta CTS */
-#define UART_MSR_ANY_DELTA \
-	(UART_MSR_DDCD | UART_MSR_TERI | UART_MSR_DDSR | UART_MSR_DCTS)
+#define UART_LSR		5    /* In:  Line Status Register */
+#define UART_LSR_FIFOE		0x80 /* Fifo error */
+#define UART_LSR_TEMT		0x40 /* Transmitter empty */
+#define UART_LSR_THRE		0x20 /* Transmit-hold-register empty */
+#define UART_LSR_BI		0x10 /* Break interrupt indicator */
+#define UART_LSR_FE		0x08 /* Frame error indicator */
+#define UART_LSR_PE		0x04 /* Parity error indicator */
+#define UART_LSR_OE		0x02 /* Overrun error indicator */
+#define UART_LSR_DR		0x01 /* Receiver data ready */
+#define UART_LSR_BRK_ERROR_BITS (UART_LSR_BI | UART_LSR_FE | UART_LSR_PE | UART_LSR_OE)
+
+#define UART_MSR	   6	/* In:  Modem Status Register */
+#define UART_MSR_DCD	   0x80 /* Data Carrier Detect */
+#define UART_MSR_RI	   0x40 /* Ring Indicator */
+#define UART_MSR_DSR	   0x20 /* Data Set Ready */
+#define UART_MSR_CTS	   0x10 /* Clear to Send */
+#define UART_MSR_DDCD	   0x08 /* Delta DCD */
+#define UART_MSR_TERI	   0x04 /* Trailing edge ring indicator */
+#define UART_MSR_DDSR	   0x02 /* Delta DSR */
+#define UART_MSR_DCTS	   0x01 /* Delta CTS */
+#define UART_MSR_ANY_DELTA (UART_MSR_DDCD | UART_MSR_TERI | UART_MSR_DDSR | UART_MSR_DCTS)
 
 #define UART_SCR 7 /* I/O: Scratch Register */
 
@@ -325,14 +321,12 @@
 #define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
 #define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
 #define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
-#define UART_RSA_SRR_Rx_TOUT \
-	(1 << 6) /* Character reception timeout occurred (1) */
-#define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */
+#define UART_RSA_SRR_Rx_TOUT	  (1 << 6) /* Character reception timeout occurred (1) */
+#define UART_RSA_SRR_TIMER	  (1 << 7) /* Timer interrupt occurred */
 
 #define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */
 
-#define UART_RSA_TIVSR \
-	((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */
+#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */
 
 #define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */