feat: add gzip and new headers

5 files changed, 65 insertions, 47 deletions

diff --git a/include/arch/x86_64/sound/asequencer.h b/include/arch/x86_64/sound/asequencer.h
index e5332cd9..61e31e42 100644
--- a/include/arch/x86_64/sound/asequencer.h
+++ b/include/arch/x86_64/sound/asequencer.h
@@ -121,7 +121,8 @@
  * event data type = snd_seq_ev_ext
  * (SNDRV_SEQ_EVENT_LENGTH_VARIABLE must be set)
  */
-#define SNDRV_SEQ_EVENT_SYSEX 130  /* system exclusive data (variable length) \
+#define SNDRV_SEQ_EVENT_SYSEX                                                 \
+	130			   /* system exclusive data (variable length) \
 				    */
 #define SNDRV_SEQ_EVENT_BOUNCE 131 /* error event */
 /* 132-134: reserved */
diff --git a/include/arch/x86_64/sound/asoc.h b/include/arch/x86_64/sound/asoc.h
index 38c6d428..5a48620a 100644
--- a/include/arch/x86_64/sound/asoc.h
+++ b/include/arch/x86_64/sound/asoc.h
@@ -520,11 +520,12 @@ struct snd_soc_tplg_pcm {
 	__le32 playback; /* supports playback mode */
 	__le32 capture;	 /* supports capture mode */
 	__le32 compress; /* 1 = compressed; 0 = PCM */
-	struct snd_soc_tplg_stream stream[SND_SOC_TPLG_STREAM_CONFIG_MAX]; /* for
-									      DAI
-									      link
-									    */
-	__le32 num_streams;			 /* number of streams */
+	struct snd_soc_tplg_stream
+		stream[SND_SOC_TPLG_STREAM_CONFIG_MAX]; /* for
+							   DAI
+							   link
+							 */
+	__le32 num_streams;				/* number of streams */
 	struct snd_soc_tplg_stream_caps caps[2]; /* playback and capture for DAI
 						  */
 	__le32 flag_mask; /* bitmask of flags to configure */
@@ -548,13 +549,14 @@ struct snd_soc_tplg_link_config {
 	char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; /* name - used to match */
 	char stream_name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; /* stream name - used
 							    to match */
-	struct snd_soc_tplg_stream stream[SND_SOC_TPLG_STREAM_CONFIG_MAX]; /* supported
-									      configs
-									      playback
-									      and
-									      captrure
-									    */
-	__le32 num_streams; /* number of streams */
+	struct snd_soc_tplg_stream
+		stream[SND_SOC_TPLG_STREAM_CONFIG_MAX]; /* supported
+							   configs
+							   playback
+							   and
+							   captrure
+							 */
+	__le32 num_streams;				/* number of streams */
 	struct snd_soc_tplg_hw_config
 		hw_config[SND_SOC_TPLG_HW_CONFIG_MAX]; /* hw configs */
 	__le32 num_hw_configs;	     /* number of hw configs */
diff --git a/include/arch/x86_64/sound/asound.h b/include/arch/x86_64/sound/asound.h
index ae70988c..46a4e3fa 100644
--- a/include/arch/x86_64/sound/asound.h
+++ b/include/arch/x86_64/sound/asound.h
@@ -178,9 +178,10 @@ typedef int __bitwise snd_pcm_access_t;
 	((snd_pcm_access_t)0) /* interleaved mmap */
 #define SNDRV_PCM_ACCESS_MMAP_NONINTERLEAVED \
 	((snd_pcm_access_t)1) /* noninterleaved mmap */
-#define SNDRV_PCM_ACCESS_MMAP_COMPLEX	((snd_pcm_access_t)2) /* complex mmap */
-#define SNDRV_PCM_ACCESS_RW_INTERLEAVED ((snd_pcm_access_t)3) /* readi/writei \
-							       */
+#define SNDRV_PCM_ACCESS_MMAP_COMPLEX ((snd_pcm_access_t)2) /* complex mmap */
+#define SNDRV_PCM_ACCESS_RW_INTERLEAVED       \
+	((snd_pcm_access_t)3) /* readi/writei \
+			       */
 #define SNDRV_PCM_ACCESS_RW_NONINTERLEAVED \
 	((snd_pcm_access_t)4) /* readn/writen */
 #define SNDRV_PCM_ACCESS_LAST SNDRV_PCM_ACCESS_RW_NONINTERLEAVED
@@ -632,8 +633,9 @@ struct __snd_pcm_mmap_control {
 };
 
 #define SNDRV_PCM_SYNC_PTR_HWSYNC (1 << 0) /* execute hwsync */
-#define SNDRV_PCM_SYNC_PTR_APPL	  (1 << 1) /* get appl_ptr from driver (r/w op) \
-					    */
+#define SNDRV_PCM_SYNC_PTR_APPL                       \
+	(1 << 1) /* get appl_ptr from driver (r/w op) \
+		  */
 #define SNDRV_PCM_SYNC_PTR_AVAIL_MIN (1 << 2) /* get avail_min from driver */
 
 struct __snd_pcm_sync_ptr {
@@ -1174,11 +1176,13 @@ struct snd_ctl_card_info {
 };
 
 typedef int __bitwise snd_ctl_elem_type_t;
-#define SNDRV_CTL_ELEM_TYPE_NONE    ((snd_ctl_elem_type_t)0) /* invalid */
-#define SNDRV_CTL_ELEM_TYPE_BOOLEAN ((snd_ctl_elem_type_t)1) /* boolean type \
-							      */
-#define SNDRV_CTL_ELEM_TYPE_INTEGER ((snd_ctl_elem_type_t)2) /* integer type \
-							      */
+#define SNDRV_CTL_ELEM_TYPE_NONE ((snd_ctl_elem_type_t)0) /* invalid */
+#define SNDRV_CTL_ELEM_TYPE_BOOLEAN              \
+	((snd_ctl_elem_type_t)1) /* boolean type \
+				  */
+#define SNDRV_CTL_ELEM_TYPE_INTEGER              \
+	((snd_ctl_elem_type_t)2) /* integer type \
+				  */
 #define SNDRV_CTL_ELEM_TYPE_ENUMERATED \
 	((snd_ctl_elem_type_t)3)			   /* enumerated type */
 #define SNDRV_CTL_ELEM_TYPE_BYTES ((snd_ctl_elem_type_t)4) /* byte array */
@@ -1189,8 +1193,9 @@ typedef int __bitwise snd_ctl_elem_type_t;
 #define SNDRV_CTL_ELEM_TYPE_LAST SNDRV_CTL_ELEM_TYPE_INTEGER64
 
 typedef int __bitwise snd_ctl_elem_iface_t;
-#define SNDRV_CTL_ELEM_IFACE_CARD ((snd_ctl_elem_iface_t)0) /* global control \
-							     */
+#define SNDRV_CTL_ELEM_IFACE_CARD                   \
+	((snd_ctl_elem_iface_t)0) /* global control \
+				   */
 #define SNDRV_CTL_ELEM_IFACE_HWDEP \
 	((snd_ctl_elem_iface_t)1) /* hardware dependent device */
 #define SNDRV_CTL_ELEM_IFACE_MIXER \
@@ -1198,8 +1203,9 @@ typedef int __bitwise snd_ctl_elem_iface_t;
 #define SNDRV_CTL_ELEM_IFACE_PCM ((snd_ctl_elem_iface_t)3) /* PCM device */
 #define SNDRV_CTL_ELEM_IFACE_RAWMIDI \
 	((snd_ctl_elem_iface_t)4) /* RawMidi device */
-#define SNDRV_CTL_ELEM_IFACE_TIMER ((snd_ctl_elem_iface_t)5) /* timer device \
-							      */
+#define SNDRV_CTL_ELEM_IFACE_TIMER                \
+	((snd_ctl_elem_iface_t)5) /* timer device \
+				   */
 #define SNDRV_CTL_ELEM_IFACE_SEQUENCER \
 	((snd_ctl_elem_iface_t)6) /* sequencer client */
 #define SNDRV_CTL_ELEM_IFACE_LAST SNDRV_CTL_ELEM_IFACE_SEQUENCER
@@ -1215,8 +1221,9 @@ typedef int __bitwise snd_ctl_elem_iface_t;
 #define SNDRV_CTL_ELEM_ACCESS_TLV_WRITE (1 << 5) /* TLV write is possible */
 #define SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE \
 	(SNDRV_CTL_ELEM_ACCESS_TLV_READ | SNDRV_CTL_ELEM_ACCESS_TLV_WRITE)
-#define SNDRV_CTL_ELEM_ACCESS_TLV_COMMAND (1 << 6) /* TLV command is possible \
-						    */
+#define SNDRV_CTL_ELEM_ACCESS_TLV_COMMAND   \
+	(1 << 6) /* TLV command is possible \
+		  */
 #define SNDRV_CTL_ELEM_ACCESS_INACTIVE \
 	(1 << 8) /* control does actually nothing, but may be updated */
 #define SNDRV_CTL_ELEM_ACCESS_LOCK  (1 << 9)  /* write lock */
diff --git a/include/arch/x86_64/sound/compress_offload.h b/include/arch/x86_64/sound/compress_offload.h
index 435fbbd8..7f7c6747 100644
--- a/include/arch/x86_64/sound/compress_offload.h
+++ b/include/arch/x86_64/sound/compress_offload.h
@@ -128,8 +128,9 @@ struct snd_compr_metadata {
 } __attribute__((packed, aligned(4)));
 
 /* flags for struct snd_compr_task */
-#define SND_COMPRESS_TFLG_NEW_STREAM (1 << 0) /* mark for the new stream data \
-					       */
+#define SND_COMPRESS_TFLG_NEW_STREAM             \
+	(1 << 0) /* mark for the new stream data \
+		  */
 
 /**
  * struct snd_compr_task - task primitive for non-realtime operation
diff --git a/include/arch/x86_64/sound/emu10k1.h b/include/arch/x86_64/sound/emu10k1.h
index 144b2449..99b2a976 100644
--- a/include/arch/x86_64/sound/emu10k1.h
+++ b/include/arch/x86_64/sound/emu10k1.h
@@ -154,9 +154,10 @@
 
 /* Each FX general purpose register is 32 bits in length, all bits are used
  */
-#define FXGPREGBASE   0x100 /* FX general purpose registers base       	*/
-#define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff \
-			     */
+#define FXGPREGBASE 0x100 /* FX general purpose registers base       	*/
+#define A_FXGPREGBASE                        \
+	0x400 /* Audigy GPRs, 0x400 to 0x5ff \
+	       */
 
 #define A_TANKMEMCTLREGBASE \
 	0x100 /* Tank memory control registers base - only for Audigy */
@@ -194,19 +195,25 @@
 #define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
 #define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
 
-#define A_GPR(x)	(A_FXGPREGBASE + (x))
-#define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf \
-							   */
-#define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f \
-							   */
-#define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf \
-							   */
-#define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f \
-							   */
-#define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf \
-							   */
-#define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f \
-							   */
+#define A_GPR(x) (A_FXGPREGBASE + (x))
+#define A_ITRAM_DATA(x)                                      \
+	(TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf \
+					   */
+#define A_ETRAM_DATA(x)                                      \
+	(TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f \
+					   */
+#define A_ITRAM_ADDR(x)                                      \
+	(TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf \
+					   */
+#define A_ETRAM_ADDR(x)                                      \
+	(TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f \
+					   */
+#define A_ITRAM_CTL(x)                                        \
+	(A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf \
+					    */
+#define A_ETRAM_CTL(x)                                        \
+	(A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f \
+					    */
 
 /* cc_reg constants */
 #define CC_REG_NORMALIZED C_00000001