diff options
Diffstat (limited to 'include/arch/x86_64/drm')
31 files changed, 704 insertions, 1344 deletions
diff --git a/include/arch/x86_64/drm/amdgpu_drm.h b/include/arch/x86_64/drm/amdgpu_drm.h index b6f422e8..086586df 100644 --- a/include/arch/x86_64/drm/amdgpu_drm.h +++ b/include/arch/x86_64/drm/amdgpu_drm.h @@ -58,55 +58,29 @@ extern "C" { #define DRM_AMDGPU_USERQ_SIGNAL 0x17 #define DRM_AMDGPU_USERQ_WAIT 0x18 -#define DRM_IOCTL_AMDGPU_GEM_CREATE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, \ - union drm_amdgpu_gem_create) -#define DRM_IOCTL_AMDGPU_GEM_MMAP \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, \ - union drm_amdgpu_gem_mmap) -#define DRM_IOCTL_AMDGPU_CTX \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) -#define DRM_IOCTL_AMDGPU_BO_LIST \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, \ - union drm_amdgpu_bo_list) -#define DRM_IOCTL_AMDGPU_CS \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) -#define DRM_IOCTL_AMDGPU_INFO \ - DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) -#define DRM_IOCTL_AMDGPU_GEM_METADATA \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, \ - struct drm_amdgpu_gem_metadata) -#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, \ - union drm_amdgpu_gem_wait_idle) -#define DRM_IOCTL_AMDGPU_GEM_VA \ - DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) -#define DRM_IOCTL_AMDGPU_WAIT_CS \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, \ - union drm_amdgpu_wait_cs) -#define DRM_IOCTL_AMDGPU_GEM_OP \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) -#define DRM_IOCTL_AMDGPU_GEM_USERPTR \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, \ - struct drm_amdgpu_gem_userptr) -#define DRM_IOCTL_AMDGPU_WAIT_FENCES \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, \ - union drm_amdgpu_wait_fences) -#define DRM_IOCTL_AMDGPU_VM \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) -#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, \ - union drm_amdgpu_fence_to_handle) -#define DRM_IOCTL_AMDGPU_SCHED \ - DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) -#define DRM_IOCTL_AMDGPU_USERQ \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq) -#define DRM_IOCTL_AMDGPU_USERQ_SIGNAL \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, \ - struct drm_amdgpu_userq_signal) -#define DRM_IOCTL_AMDGPU_USERQ_WAIT \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, \ - struct drm_amdgpu_userq_wait) +#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) +#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) +#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) +#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) +#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) +#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) +#define DRM_IOCTL_AMDGPU_GEM_METADATA \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) +#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) +#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) +#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) +#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) +#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) +#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) +#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) +#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) +#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) +#define DRM_IOCTL_AMDGPU_USERQ DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq) +#define DRM_IOCTL_AMDGPU_USERQ_SIGNAL \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal) +#define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait) /** * DOC: memory domains @@ -141,11 +115,9 @@ extern "C" { #define AMDGPU_GEM_DOMAIN_GWS 0x10 #define AMDGPU_GEM_DOMAIN_OA 0x20 #define AMDGPU_GEM_DOMAIN_DOORBELL 0x40 -#define AMDGPU_GEM_DOMAIN_MASK \ - (AMDGPU_GEM_DOMAIN_CPU | AMDGPU_GEM_DOMAIN_GTT | \ - AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GDS | \ - AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | \ - AMDGPU_GEM_DOMAIN_DOORBELL) +#define AMDGPU_GEM_DOMAIN_MASK \ + (AMDGPU_GEM_DOMAIN_CPU | AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GDS | \ + AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | AMDGPU_GEM_DOMAIN_DOORBELL) /* Flag that CPU access will be required for the case of VRAM domain */ #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) @@ -714,14 +686,11 @@ struct drm_amdgpu_gem_userptr { #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7 /* These are DCC recompression settings for memory management: */ #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3 -#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK \ - 0x3 /* 0:64B, 1:128B, 2:256B */ -#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5 -#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK \ - 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */ -#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8 -#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK \ - 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */ +#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */ +#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5 +#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */ +#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8 +#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */ /* When clearing the buffer or moving it from VRAM to GTT, don't compress and * set DCC metadata to uncompressed. Set when parts of an allocation bypass DCC * and read raw data. */ @@ -732,12 +701,10 @@ struct drm_amdgpu_gem_userptr { #define AMDGPU_TILING_GFX12_SCANOUT_MASK 0x1 /* Set/Get helpers for tiling flags. */ -#define AMDGPU_TILING_SET(field, value) \ - (((__u64)(value) & AMDGPU_TILING_##field##_MASK) \ - << AMDGPU_TILING_##field##_SHIFT) -#define AMDGPU_TILING_GET(value, field) \ - (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & \ - AMDGPU_TILING_##field##_MASK) +#define AMDGPU_TILING_SET(field, value) \ + (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) +#define AMDGPU_TILING_GET(value, field) \ + (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 @@ -1566,8 +1533,7 @@ struct drm_amdgpu_info_vce_clock_table_entry { }; struct drm_amdgpu_info_vce_clock_table { - struct drm_amdgpu_info_vce_clock_table_entry - entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; + struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; __u32 num_valid_entries; __u32 pad; }; @@ -1593,8 +1559,7 @@ struct drm_amdgpu_info_video_codec_info { }; struct drm_amdgpu_info_video_caps { - struct drm_amdgpu_info_video_codec_info - codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; + struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; }; #define AMDGPU_VMHUB_TYPE_MASK 0xff diff --git a/include/arch/x86_64/drm/amdxdna_accel.h b/include/arch/x86_64/drm/amdxdna_accel.h index 75b74e1d..4064d731 100644 --- a/include/arch/x86_64/drm/amdxdna_accel.h +++ b/include/arch/x86_64/drm/amdxdna_accel.h @@ -464,41 +464,27 @@ struct amdxdna_drm_set_power_mode { __u8 pad[7]; }; -#define DRM_IOCTL_AMDXDNA_CREATE_HWCTX \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_HWCTX, \ - struct amdxdna_drm_create_hwctx) +#define DRM_IOCTL_AMDXDNA_CREATE_HWCTX \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_HWCTX, struct amdxdna_drm_create_hwctx) -#define DRM_IOCTL_AMDXDNA_DESTROY_HWCTX \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_DESTROY_HWCTX, \ - struct amdxdna_drm_destroy_hwctx) +#define DRM_IOCTL_AMDXDNA_DESTROY_HWCTX \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_DESTROY_HWCTX, struct amdxdna_drm_destroy_hwctx) -#define DRM_IOCTL_AMDXDNA_CONFIG_HWCTX \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CONFIG_HWCTX, \ - struct amdxdna_drm_config_hwctx) +#define DRM_IOCTL_AMDXDNA_CONFIG_HWCTX \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CONFIG_HWCTX, struct amdxdna_drm_config_hwctx) -#define DRM_IOCTL_AMDXDNA_CREATE_BO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_BO, \ - struct amdxdna_drm_create_bo) +#define DRM_IOCTL_AMDXDNA_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_BO, struct amdxdna_drm_create_bo) -#define DRM_IOCTL_AMDXDNA_GET_BO_INFO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_BO_INFO, \ - struct amdxdna_drm_get_bo_info) +#define DRM_IOCTL_AMDXDNA_GET_BO_INFO \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_BO_INFO, struct amdxdna_drm_get_bo_info) -#define DRM_IOCTL_AMDXDNA_SYNC_BO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SYNC_BO, \ - struct amdxdna_drm_sync_bo) +#define DRM_IOCTL_AMDXDNA_SYNC_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SYNC_BO, struct amdxdna_drm_sync_bo) -#define DRM_IOCTL_AMDXDNA_EXEC_CMD \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_EXEC_CMD, \ - struct amdxdna_drm_exec_cmd) +#define DRM_IOCTL_AMDXDNA_EXEC_CMD DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_EXEC_CMD, struct amdxdna_drm_exec_cmd) -#define DRM_IOCTL_AMDXDNA_GET_INFO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_INFO, \ - struct amdxdna_drm_get_info) +#define DRM_IOCTL_AMDXDNA_GET_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_INFO, struct amdxdna_drm_get_info) -#define DRM_IOCTL_AMDXDNA_SET_STATE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SET_STATE, \ - struct amdxdna_drm_set_state) +#define DRM_IOCTL_AMDXDNA_SET_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SET_STATE, struct amdxdna_drm_set_state) #if defined(__cplusplus) } /* extern c end */ diff --git a/include/arch/x86_64/drm/armada_drm.h b/include/arch/x86_64/drm/armada_drm.h index 449c9b4f..88d398bf 100644 --- a/include/arch/x86_64/drm/armada_drm.h +++ b/include/arch/x86_64/drm/armada_drm.h @@ -20,8 +20,7 @@ extern "C" { #define DRM_ARMADA_GEM_MMAP 0x02 #define DRM_ARMADA_GEM_PWRITE 0x03 -#define ARMADA_IOCTL(dir, name, str) \ - DRM_##dir(DRM_COMMAND_BASE + DRM_ARMADA_##name, struct drm_armada_##str) +#define ARMADA_IOCTL(dir, name, str) DRM_##dir(DRM_COMMAND_BASE + DRM_ARMADA_##name, struct drm_armada_##str) struct drm_armada_gem_create { __u32 handle; diff --git a/include/arch/x86_64/drm/asahi_drm.h b/include/arch/x86_64/drm/asahi_drm.h index bda7ce43..4567b981 100644 --- a/include/arch/x86_64/drm/asahi_drm.h +++ b/include/arch/x86_64/drm/asahi_drm.h @@ -1168,9 +1168,8 @@ struct drm_asahi_get_time { * * Return: An IOCTL number to be passed to ioctl() from userspace. */ -#define DRM_IOCTL_ASAHI(__access, __id, __type) \ - DRM_IO##__access(DRM_COMMAND_BASE + DRM_ASAHI_##__id, \ - struct drm_asahi_##__type) +#define DRM_IOCTL_ASAHI(__access, __id, __type) \ + DRM_IO##__access(DRM_COMMAND_BASE + DRM_ASAHI_##__id, struct drm_asahi_##__type) /* Note: this is an enum so that it can be resolved by Rust bindgen. */ enum { @@ -1179,16 +1178,11 @@ enum { DRM_IOCTL_ASAHI_VM_CREATE = DRM_IOCTL_ASAHI(WR, VM_CREATE, vm_create), DRM_IOCTL_ASAHI_VM_DESTROY = DRM_IOCTL_ASAHI(W, VM_DESTROY, vm_destroy), DRM_IOCTL_ASAHI_VM_BIND = DRM_IOCTL_ASAHI(W, VM_BIND, vm_bind), - DRM_IOCTL_ASAHI_GEM_CREATE = - DRM_IOCTL_ASAHI(WR, GEM_CREATE, gem_create), - DRM_IOCTL_ASAHI_GEM_MMAP_OFFSET = - DRM_IOCTL_ASAHI(WR, GEM_MMAP_OFFSET, gem_mmap_offset), - DRM_IOCTL_ASAHI_GEM_BIND_OBJECT = - DRM_IOCTL_ASAHI(WR, GEM_BIND_OBJECT, gem_bind_object), - DRM_IOCTL_ASAHI_QUEUE_CREATE = - DRM_IOCTL_ASAHI(WR, QUEUE_CREATE, queue_create), - DRM_IOCTL_ASAHI_QUEUE_DESTROY = - DRM_IOCTL_ASAHI(W, QUEUE_DESTROY, queue_destroy), + DRM_IOCTL_ASAHI_GEM_CREATE = DRM_IOCTL_ASAHI(WR, GEM_CREATE, gem_create), + DRM_IOCTL_ASAHI_GEM_MMAP_OFFSET = DRM_IOCTL_ASAHI(WR, GEM_MMAP_OFFSET, gem_mmap_offset), + DRM_IOCTL_ASAHI_GEM_BIND_OBJECT = DRM_IOCTL_ASAHI(WR, GEM_BIND_OBJECT, gem_bind_object), + DRM_IOCTL_ASAHI_QUEUE_CREATE = DRM_IOCTL_ASAHI(WR, QUEUE_CREATE, queue_create), + DRM_IOCTL_ASAHI_QUEUE_DESTROY = DRM_IOCTL_ASAHI(W, QUEUE_DESTROY, queue_destroy), DRM_IOCTL_ASAHI_SUBMIT = DRM_IOCTL_ASAHI(W, SUBMIT, submit), }; diff --git a/include/arch/x86_64/drm/drm.h b/include/arch/x86_64/drm/drm.h index a928f61f..7ba7a721 100644 --- a/include/arch/x86_64/drm/drm.h +++ b/include/arch/x86_64/drm/drm.h @@ -167,12 +167,7 @@ struct drm_block { * \sa drmCtlInstHandler() and drmCtlUninstHandler(). */ struct drm_control { - enum { - DRM_ADD_COMMAND, - DRM_RM_COMMAND, - DRM_INST_HANDLER, - DRM_UNINST_HANDLER - } func; + enum { DRM_ADD_COMMAND, DRM_RM_COMMAND, DRM_INST_HANDLER, DRM_UNINST_HANDLER } func; int irq; }; @@ -214,9 +209,9 @@ struct drm_ctx_priv_map { * \sa drmAddMap(). */ struct drm_map { - unsigned long offset; /**< Requested physical address (0 for SAREA)*/ - unsigned long size; /**< Requested physical size (bytes) */ - enum drm_map_type type; /**< Type of memory to map */ + unsigned long offset; /**< Requested physical address (0 for SAREA)*/ + unsigned long size; /**< Requested physical size (bytes) */ + enum drm_map_type type; /**< Type of memory to map */ enum drm_map_flags flags; /**< Flags */ void *handle; /**< User-space: "Handle" to pass to mmap() */ /**< Kernel-space: kernel-virtual address */ @@ -253,7 +248,7 @@ enum drm_stat_type { _DRM_STAT_DMA, /**< DMA */ _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ _DRM_STAT_MISSED /**< Missed DMA opportunity */ - /* Add to the *END* of the list */ + /* Add to the *END* of the list */ }; /* @@ -332,10 +327,10 @@ struct drm_buf_desc { int low_mark; /**< Low water mark */ int high_mark; /**< High water mark */ enum { - _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ - _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ - _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ - _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ + _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ + _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ + _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ + _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ } flags; unsigned long agp_start; /**< @@ -405,10 +400,7 @@ struct drm_dma { int granted_count; /**< Number of buffers granted */ }; -enum drm_ctx_flags { - _DRM_CONTEXT_PRESERVED = 0x01, - _DRM_CONTEXT_2DONLY = 0x02 -}; +enum drm_ctx_flags { _DRM_CONTEXT_PRESERVED = 0x01, _DRM_CONTEXT_2DONLY = 0x02 }; /* * DRM_IOCTL_ADD_CTX ioctl argument type. @@ -472,20 +464,18 @@ enum drm_vblank_seq_type { _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ /* bits 1-6 are reserved for high crtcs */ _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e, - _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */ - _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ + _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */ + _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ - _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ - _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, - unsupported */ + _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ + _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, + unsupported */ }; #define _DRM_VBLANK_HIGH_CRTC_SHIFT 1 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) -#define _DRM_VBLANK_FLAGS_MASK \ - (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \ - _DRM_VBLANK_NEXTONMISS) +#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS) struct drm_wait_vblank_request { enum drm_vblank_seq_type type; @@ -925,10 +915,8 @@ struct drm_syncobj_transfer { #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0) #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1) -#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE \ - (1 << 2) /* wait for time point to become available */ -#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_DEADLINE \ - (1 << 3) /* set fence deadline to deadline_nsec */ +#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point to become available */ +#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_DEADLINE (1 << 3) /* set fence deadline to deadline_nsec */ struct drm_syncobj_wait { __u64 handles; /* absolute timeout */ @@ -994,8 +982,7 @@ struct drm_syncobj_array { __u32 pad; }; -#define DRM_SYNCOBJ_QUERY_FLAGS_LAST_SUBMITTED \ - (1 << 0) /* last available point on timeline syncobj */ +#define DRM_SYNCOBJ_QUERY_FLAGS_LAST_SUBMITTED (1 << 0) /* last available point on timeline syncobj */ struct drm_syncobj_timeline_array { __u64 handles; __u64 points; @@ -1015,16 +1002,14 @@ struct drm_crtc_get_sequence { * when the first pixel of the refresh cycle leaves the display engine * for the display */ -#define DRM_CRTC_SEQUENCE_RELATIVE \ - 0x00000001 /* sequence is relative to current */ -#define DRM_CRTC_SEQUENCE_NEXT_ON_MISS \ - 0x00000002 /* Use next sequence if we've missed */ +#define DRM_CRTC_SEQUENCE_RELATIVE 0x00000001 /* sequence is relative to current */ +#define DRM_CRTC_SEQUENCE_NEXT_ON_MISS 0x00000002 /* Use next sequence if we've missed */ struct drm_crtc_queue_sequence { __u32 crtc_id; __u32 flags; - __u64 sequence; /* on input, target sequence. on output, actual sequence - */ + __u64 sequence; /* on input, target sequence. on output, actual sequence + */ __u64 user_data; /* user data passed to event */ }; @@ -1159,9 +1144,8 @@ extern "C" { #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) -#define DRM_IOCTL_CRTC_GET_SEQUENCE DRM_IOWR(0x3b, struct drm_crtc_get_sequence) -#define DRM_IOCTL_CRTC_QUEUE_SEQUENCE \ - DRM_IOWR(0x3c, struct drm_crtc_queue_sequence) +#define DRM_IOCTL_CRTC_GET_SEQUENCE DRM_IOWR(0x3b, struct drm_crtc_get_sequence) +#define DRM_IOCTL_CRTC_QUEUE_SEQUENCE DRM_IOWR(0x3c, struct drm_crtc_queue_sequence) #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) @@ -1172,8 +1156,7 @@ extern "C" { #define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut) #define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut) #define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder) -#define DRM_IOCTL_MODE_GETCONNECTOR \ - DRM_IOWR(0xA7, struct drm_mode_get_connector) +#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector) #define DRM_IOCTL_MODE_ATTACHMODE \ DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) \ */ @@ -1182,8 +1165,7 @@ extern "C" { */ #define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property) -#define DRM_IOCTL_MODE_SETPROPERTY \ - DRM_IOWR(0xAB, struct drm_mode_connector_set_property) +#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property) #define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) #define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) #define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) @@ -1221,24 +1203,19 @@ extern "C" { * &DRM_CAP_DUMB_PREFERRED_DEPTH and &DRM_CAP_DUMB_PREFER_SHADOW indicate * driver preferences for dumb buffers. */ -#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb) -#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb) -#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb) -#define DRM_IOCTL_MODE_GETPLANERESOURCES \ - DRM_IOWR(0xB5, struct drm_mode_get_plane_res) -#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane) -#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane) -#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2) -#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES \ - DRM_IOWR(0xB9, struct drm_mode_obj_get_properties) -#define DRM_IOCTL_MODE_OBJ_SETPROPERTY \ - DRM_IOWR(0xBA, struct drm_mode_obj_set_property) -#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2) -#define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic) -#define DRM_IOCTL_MODE_CREATEPROPBLOB \ - DRM_IOWR(0xBD, struct drm_mode_create_blob) -#define DRM_IOCTL_MODE_DESTROYPROPBLOB \ - DRM_IOWR(0xBE, struct drm_mode_destroy_blob) +#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb) +#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb) +#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb) +#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res) +#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane) +#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane) +#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2) +#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties) +#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property) +#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2) +#define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic) +#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob) +#define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob) #define DRM_IOCTL_SYNCOBJ_CREATE DRM_IOWR(0xBF, struct drm_syncobj_create) #define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy) @@ -1253,13 +1230,10 @@ extern "C" { #define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease) #define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease) -#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT \ - DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait) -#define DRM_IOCTL_SYNCOBJ_QUERY \ - DRM_IOWR(0xCB, struct drm_syncobj_timeline_array) -#define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer) -#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL \ - DRM_IOWR(0xCD, struct drm_syncobj_timeline_array) +#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait) +#define DRM_IOCTL_SYNCOBJ_QUERY DRM_IOWR(0xCB, struct drm_syncobj_timeline_array) +#define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer) +#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array) /** * DRM_IOCTL_MODE_GETFB2 - Get framebuffer metadata. diff --git a/include/arch/x86_64/drm/drm_fourcc.h b/include/arch/x86_64/drm/drm_fourcc.h index b37e02b3..0f3d05c0 100644 --- a/include/arch/x86_64/drm/drm_fourcc.h +++ b/include/arch/x86_64/drm/drm_fourcc.h @@ -102,12 +102,9 @@ extern "C" { * stacks should approve additions. */ -#define fourcc_code(a, b, c, d) \ - ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | \ - ((__u32)(d) << 24)) +#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | ((__u32)(d) << 24)) -#define DRM_FORMAT_BIG_ENDIAN \ - (1U << 31) /* format is big endian instead of little endian */ +#define DRM_FORMAT_BIG_ENDIAN (1U << 31) /* format is big endian instead of little endian */ /* Reserve 0 for the invalid format specifier */ #define DRM_FORMAT_INVALID 0 @@ -117,11 +114,10 @@ extern "C" { fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 \ 1:1:1:1:1:1:1:1 eight pixels/byte \ */ -#define DRM_FORMAT_C2 \ - fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four \ - pixels/byte */ -#define DRM_FORMAT_C4 \ - fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */ +#define DRM_FORMAT_C2 \ + fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four \ + pixels/byte */ +#define DRM_FORMAT_C4 fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */ #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ /* 1 bpp Darkness (inverse relationship between channel value and brightness) */ @@ -136,8 +132,7 @@ extern "C" { pixels/byte */ /* 4 bpp Darkness (inverse relationship between channel value and brightness) */ -#define DRM_FORMAT_D4 \ - fourcc_code('D', '4', ' ', ' ') /* [7:0] D0:D1 4:4 two pixels/byte */ +#define DRM_FORMAT_D4 fourcc_code('D', '4', ' ', ' ') /* [7:0] D0:D1 4:4 two pixels/byte */ /* 8 bpp Darkness (inverse relationship between channel value and brightness) */ #define DRM_FORMAT_D8 fourcc_code('D', '8', ' ', ' ') /* [7:0] D */ @@ -154,41 +149,31 @@ extern "C" { pixels/byte */ /* 4 bpp Red (direct relationship between channel value and brightness) */ -#define DRM_FORMAT_R4 \ - fourcc_code('R', '4', ' ', ' ') /* [7:0] R0:R1 4:4 two pixels/byte */ +#define DRM_FORMAT_R4 fourcc_code('R', '4', ' ', ' ') /* [7:0] R0:R1 4:4 two pixels/byte */ /* 8 bpp Red (direct relationship between channel value and brightness) */ #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ /* 10 bpp Red (direct relationship between channel value and brightness) */ -#define DRM_FORMAT_R10 \ - fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */ +#define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */ /* 12 bpp Red (direct relationship between channel value and brightness) */ -#define DRM_FORMAT_R12 \ - fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */ +#define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */ /* 16 bpp Red (direct relationship between channel value and brightness) */ -#define DRM_FORMAT_R16 \ - fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ +#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ /* 16 bpp RG */ -#define DRM_FORMAT_RG88 \ - fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ -#define DRM_FORMAT_GR88 \ - fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ +#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ +#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ /* 32 bpp RG */ -#define DRM_FORMAT_RG1616 \ - fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ -#define DRM_FORMAT_GR1616 \ - fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ +#define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ +#define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ /* 8 bpp RGB */ -#define DRM_FORMAT_RGB332 \ - fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ -#define DRM_FORMAT_BGR233 \ - fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ +#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ +#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ /* 16 bpp RGB */ #define DRM_FORMAT_XRGB4444 \ @@ -243,16 +228,12 @@ extern "C" { fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little \ endian */ -#define DRM_FORMAT_RGB565 \ - fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ -#define DRM_FORMAT_BGR565 \ - fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ +#define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ +#define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ /* 24 bpp RGB */ -#define DRM_FORMAT_RGB888 \ - fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ -#define DRM_FORMAT_BGR888 \ - fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ +#define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ +#define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ /* 32 bpp RGB */ #define DRM_FORMAT_XRGB8888 \ @@ -349,10 +330,8 @@ extern "C" { fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little \ endian */ -#define DRM_FORMAT_R16F \ - fourcc_code('R', ' ', ' ', 'H') /* [15:0] R 16 little endian */ -#define DRM_FORMAT_GR1616F \ - fourcc_code('G', 'R', ' ', 'H') /* [31:0] G:R 16:16 little endian */ +#define DRM_FORMAT_R16F fourcc_code('R', ' ', ' ', 'H') /* [15:0] R 16 little endian */ +#define DRM_FORMAT_GR1616F fourcc_code('G', 'R', ' ', 'H') /* [31:0] G:R 16:16 little endian */ #define DRM_FORMAT_BGR161616F \ fourcc_code('B', 'G', 'R', 'H') /* [47:0] B:G:R 16:16:16 little endian \ */ @@ -362,10 +341,8 @@ extern "C" { * IEEE 754-2008 binary32 float * [31:0] sign:exponent:mantissa 1:8:23 */ -#define DRM_FORMAT_R32F \ - fourcc_code('R', ' ', ' ', 'F') /* [31:0] R 32 little endian */ -#define DRM_FORMAT_GR3232F \ - fourcc_code('G', 'R', ' ', 'F') /* [63:0] R:G 32:32 little endian */ +#define DRM_FORMAT_R32F fourcc_code('R', ' ', ' ', 'F') /* [31:0] R 32 little endian */ +#define DRM_FORMAT_GR3232F fourcc_code('G', 'R', ' ', 'F') /* [63:0] R:G 32:32 little endian */ #define DRM_FORMAT_BGR323232F \ fourcc_code('B', 'G', 'R', 'F') /* [95:0] R:G:B 32:32:32 little endian \ */ @@ -505,29 +482,20 @@ extern "C" { * or * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian */ -#define DRM_FORMAT_NV12 \ - fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ -#define DRM_FORMAT_NV21 \ - fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ -#define DRM_FORMAT_NV16 \ - fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ -#define DRM_FORMAT_NV61 \ - fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ -#define DRM_FORMAT_NV24 \ - fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ -#define DRM_FORMAT_NV42 \ - fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ +#define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ +#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ +#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ /* * 2 plane YCbCr * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian */ -#define DRM_FORMAT_NV15 \ - fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ -#define DRM_FORMAT_NV20 \ - fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */ -#define DRM_FORMAT_NV30 \ - fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */ /* * 2 plane YCbCr MSB aligned @@ -717,12 +685,9 @@ extern "C" { #define fourcc_mod_get_vendor(modifier) (((modifier) >> 56) & 0xff) -#define fourcc_mod_is_vendor(modifier, vendor) \ - (fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_##vendor) +#define fourcc_mod_is_vendor(modifier, vendor) (fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_##vendor) -#define fourcc_mod_code(vendor, val) \ - ((((__u64)DRM_FORMAT_MOD_VENDOR_##vendor) << 56) | \ - ((val) & 0x00ffffffffffffffULL)) +#define fourcc_mod_code(vendor, val) ((((__u64)DRM_FORMAT_MOD_VENDOR_##vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) /* * Format Modifier tokens: @@ -1242,10 +1207,9 @@ extern "C" { * * 55:28 - Reserved for future use. Must be zero. */ -#define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ - fourcc_mod_code(NVIDIA, (0x10 | ((h) & 0xf) | (((k) & 0xff) << 12) | \ - (((g) & 0x3) << 20) | (((s) & 0x1) << 22) | \ - (((s) & 0x6) << 25) | (((c) & 0x7) << 23))) +#define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ + fourcc_mod_code(NVIDIA, (0x10 | ((h) & 0xf) | (((k) & 0xff) << 12) | (((g) & 0x3) << 20) | \ + (((s) & 0x1) << 22) | (((s) & 0x6) << 25) | (((c) & 0x7) << 23))) /* To grandfather in prior block linear format modifiers to the above layout, * the page kind "0", which corresponds to "pitch/linear" and hence is unusable @@ -1253,8 +1217,7 @@ extern "C" { * which corresponds to the "generic" kind used for simple single-sample * uncompressed color formats on Fermi - Volta GPUs. */ -static __inline__ __u64 -drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) +static __inline__ __u64 drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) { if (!(modifier & 0x10) || (modifier & (0xff << 12))) return modifier; @@ -1283,21 +1246,14 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format * in full detail. */ -#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ - DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v)) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v)) -#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ - DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) -#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ - DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) -#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ - DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) -#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ - DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) -#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ - DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) -#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ - DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) /* * Some Broadcom modifiers take parameters, for example the number of @@ -1307,16 +1263,12 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) */ #define __fourcc_mod_broadcom_param_shift 8 #define __fourcc_mod_broadcom_param_bits 48 -#define fourcc_mod_broadcom_code(val, params) \ - fourcc_mod_code(BROADCOM, ((((__u64)params) \ - << __fourcc_mod_broadcom_param_shift) | \ - val)) -#define fourcc_mod_broadcom_param(m) \ - ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ - ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) -#define fourcc_mod_broadcom_mod(m) \ - ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) \ - << __fourcc_mod_broadcom_param_shift)) +#define fourcc_mod_broadcom_code(val, params) \ + fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val)) +#define fourcc_mod_broadcom_param(m) \ + ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) +#define fourcc_mod_broadcom_mod(m) \ + ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << __fourcc_mod_broadcom_param_shift)) /* * Broadcom VC4 "T" format @@ -1367,23 +1319,15 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) * wide, but as this is a 10 bpp format that translates to 96 pixels. */ -#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ - fourcc_mod_broadcom_code(2, v) -#define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ - fourcc_mod_broadcom_code(3, v) -#define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ - fourcc_mod_broadcom_code(4, v) -#define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ - fourcc_mod_broadcom_code(5, v) - -#define DRM_FORMAT_MOD_BROADCOM_SAND32 \ - DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) -#define DRM_FORMAT_MOD_BROADCOM_SAND64 \ - DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) -#define DRM_FORMAT_MOD_BROADCOM_SAND128 \ - DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) -#define DRM_FORMAT_MOD_BROADCOM_SAND256 \ - DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) +#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) fourcc_mod_broadcom_code(2, v) +#define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) fourcc_mod_broadcom_code(3, v) +#define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) fourcc_mod_broadcom_code(4, v) +#define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) fourcc_mod_broadcom_code(5, v) + +#define DRM_FORMAT_MOD_BROADCOM_SAND32 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) +#define DRM_FORMAT_MOD_BROADCOM_SAND64 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) +#define DRM_FORMAT_MOD_BROADCOM_SAND128 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) +#define DRM_FORMAT_MOD_BROADCOM_SAND256 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) /* Broadcom UIF format * @@ -1427,15 +1371,13 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of * sixteen different categories. */ -#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ - fourcc_mod_code(ARM, ((__u64)(__type) << 52) | \ - ((__val) & 0x000fffffffffffffULL)) +#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ + fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01 -#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ - DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) +#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) /* * AFBC superblock size @@ -1606,8 +1548,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) #define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02 -#define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \ - DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode) +#define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode) /* * AFRC coding unit size modifier. @@ -1656,8 +1597,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels * in the block are reordered. */ -#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ - DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) +#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) /* * Allwinner tiled modifier @@ -1698,12 +1638,10 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) #define __fourcc_mod_amlogic_options_shift 8 #define __fourcc_mod_amlogic_options_mask 0xff -#define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \ - fourcc_mod_code( \ - AMLOGIC, \ - ((__layout) & __fourcc_mod_amlogic_layout_mask) | \ - (((__options) & __fourcc_mod_amlogic_options_mask) \ - << __fourcc_mod_amlogic_options_shift)) +#define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \ + fourcc_mod_code(AMLOGIC, ((__layout) & __fourcc_mod_amlogic_layout_mask) | \ + (((__options) & __fourcc_mod_amlogic_options_mask) \ + << __fourcc_mod_amlogic_options_shift)) /* Amlogic FBC Layouts */ @@ -1792,8 +1730,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) #define MTK_FMT_MOD_10BIT_LAYOUT_LSBRASTER (0x2 << 16) /* alias for the most common tiling format */ -#define DRM_FORMAT_MOD_MTK_16L_32S_TILE \ - DRM_FORMAT_MOD_MTK(MTK_FMT_MOD_TILE_16L32S) +#define DRM_FORMAT_MOD_MTK_16L_32S_TILE DRM_FORMAT_MOD_MTK(MTK_FMT_MOD_TILE_16L32S) /* * Apple GPU-tiled layouts. @@ -1988,12 +1925,9 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) #define AMD_FMT_MOD_PIPE_SHIFT 33 #define AMD_FMT_MOD_PIPE_MASK 0x7 -#define AMD_FMT_MOD_SET(field, value) \ - ((__u64)(value) << AMD_FMT_MOD_##field##_SHIFT) -#define AMD_FMT_MOD_GET(field, value) \ - (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) -#define AMD_FMT_MOD_CLEAR(field) \ - (~((__u64)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) +#define AMD_FMT_MOD_SET(field, value) ((__u64)(value) << AMD_FMT_MOD_##field##_SHIFT) +#define AMD_FMT_MOD_GET(field, value) (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) +#define AMD_FMT_MOD_CLEAR(field) (~((__u64)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) #if defined(__cplusplus) } diff --git a/include/arch/x86_64/drm/drm_mode.h b/include/arch/x86_64/drm/drm_mode.h index 8517ff0c..8881cfc1 100644 --- a/include/arch/x86_64/drm/drm_mode.h +++ b/include/arch/x86_64/drm/drm_mode.h @@ -46,9 +46,8 @@ extern "C" { #define DRM_DISPLAY_MODE_LEN 32 #define DRM_PROP_NAME_LEN 32 -#define DRM_MODE_TYPE_BUILTIN (1 << 0) /* deprecated */ -#define DRM_MODE_TYPE_CLOCK_C \ - ((1 << 1) | DRM_MODE_TYPE_BUILTIN) /* deprecated */ +#define DRM_MODE_TYPE_BUILTIN (1 << 0) /* deprecated */ +#define DRM_MODE_TYPE_CLOCK_C ((1 << 1) | DRM_MODE_TYPE_BUILTIN) /* deprecated */ #define DRM_MODE_TYPE_CRTC_C \ ((1 << 2) | DRM_MODE_TYPE_BUILTIN) /* deprecated \ */ @@ -57,8 +56,7 @@ extern "C" { #define DRM_MODE_TYPE_USERDEF (1 << 5) #define DRM_MODE_TYPE_DRIVER (1 << 6) -#define DRM_MODE_TYPE_ALL \ - (DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_USERDEF | DRM_MODE_TYPE_DRIVER) +#define DRM_MODE_TYPE_ALL (DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_USERDEF | DRM_MODE_TYPE_DRIVER) /* Video mode flags */ /* bit compatible with the xrandr RR_ definitions (bits 0-13) @@ -121,12 +119,11 @@ extern "C" { #define DRM_MODE_FLAG_PIC_AR_64_27 (DRM_MODE_PICTURE_ASPECT_64_27 << 19) #define DRM_MODE_FLAG_PIC_AR_256_135 (DRM_MODE_PICTURE_ASPECT_256_135 << 19) -#define DRM_MODE_FLAG_ALL \ - (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC | \ - DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE | \ - DRM_MODE_FLAG_DBLSCAN | DRM_MODE_FLAG_CSYNC | DRM_MODE_FLAG_PCSYNC | \ - DRM_MODE_FLAG_NCSYNC | DRM_MODE_FLAG_HSKEW | DRM_MODE_FLAG_DBLCLK | \ - DRM_MODE_FLAG_CLKDIV2 | DRM_MODE_FLAG_3D_MASK) +#define DRM_MODE_FLAG_ALL \ + (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC | \ + DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLSCAN | DRM_MODE_FLAG_CSYNC | DRM_MODE_FLAG_PCSYNC | \ + DRM_MODE_FLAG_NCSYNC | DRM_MODE_FLAG_HSKEW | DRM_MODE_FLAG_DBLCLK | DRM_MODE_FLAG_CLKDIV2 | \ + DRM_MODE_FLAG_3D_MASK) /* DPMS flags */ /* bit compatible with the xorg definitions. */ @@ -176,9 +173,7 @@ extern "C" { * * Bitmask used to look for drm plane rotations. */ -#define DRM_MODE_ROTATE_MASK \ - (DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | \ - DRM_MODE_ROTATE_270) +#define DRM_MODE_ROTATE_MASK (DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270) /* * DRM_MODE_REFLECT_<axis> @@ -510,9 +505,8 @@ struct drm_mode_get_connector { #define DRM_MODE_PROP_BITMASK (1 << 5) /* bitmask of enumerated types */ /* non-extended types: legacy bitmask, one bit per type: */ -#define DRM_MODE_PROP_LEGACY_TYPE \ - (DRM_MODE_PROP_RANGE | DRM_MODE_PROP_ENUM | DRM_MODE_PROP_BLOB | \ - DRM_MODE_PROP_BITMASK) +#define DRM_MODE_PROP_LEGACY_TYPE \ + (DRM_MODE_PROP_RANGE | DRM_MODE_PROP_ENUM | DRM_MODE_PROP_BLOB | DRM_MODE_PROP_BITMASK) /* extended-types: rather than continue to consume a bit per type, * grab a chunk of the bits to use as integer type id. @@ -968,17 +962,13 @@ struct hdr_output_metadata { #define DRM_MODE_PAGE_FLIP_ASYNC 0x02 #define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4 #define DRM_MODE_PAGE_FLIP_TARGET_RELATIVE 0x8 -#define DRM_MODE_PAGE_FLIP_TARGET \ - (DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE | \ - DRM_MODE_PAGE_FLIP_TARGET_RELATIVE) +#define DRM_MODE_PAGE_FLIP_TARGET (DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE | DRM_MODE_PAGE_FLIP_TARGET_RELATIVE) /** * DRM_MODE_PAGE_FLIP_FLAGS * * Bitmask of flags suitable for &drm_mode_crtc_page_flip_target.flags. */ -#define DRM_MODE_PAGE_FLIP_FLAGS \ - (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | \ - DRM_MODE_PAGE_FLIP_TARGET) +#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | DRM_MODE_PAGE_FLIP_TARGET) /* * Request a page flip on the specified crtc. @@ -1128,9 +1118,8 @@ struct drm_mode_destroy_dumb { * Bitfield of flags accepted by the &DRM_IOCTL_MODE_ATOMIC IOCTL in * &drm_mode_atomic.flags. */ -#define DRM_MODE_ATOMIC_FLAGS \ - (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | \ - DRM_MODE_ATOMIC_TEST_ONLY | DRM_MODE_ATOMIC_NONBLOCK | \ +#define DRM_MODE_ATOMIC_FLAGS \ + (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | DRM_MODE_ATOMIC_TEST_ONLY | DRM_MODE_ATOMIC_NONBLOCK | \ DRM_MODE_ATOMIC_ALLOW_MODESET) struct drm_mode_atomic { diff --git a/include/arch/x86_64/drm/drm_sarea.h b/include/arch/x86_64/drm/drm_sarea.h index 645d4925..0bd4c1f0 100644 --- a/include/arch/x86_64/drm/drm_sarea.h +++ b/include/arch/x86_64/drm/drm_sarea.h @@ -79,7 +79,7 @@ struct drm_sarea { struct drm_sarea_drawable drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */ - struct drm_sarea_frame frame; /**< frame */ + struct drm_sarea_frame frame; /**< frame */ drm_context_t dummy_context; }; diff --git a/include/arch/x86_64/drm/etnaviv_drm.h b/include/arch/x86_64/drm/etnaviv_drm.h index 7ed02dcc..dba78b7f 100644 --- a/include/arch/x86_64/drm/etnaviv_drm.h +++ b/include/arch/x86_64/drm/etnaviv_drm.h @@ -187,9 +187,8 @@ struct drm_etnaviv_gem_submit_pmr { #define ETNA_SUBMIT_FENCE_FD_IN 0x0002 #define ETNA_SUBMIT_FENCE_FD_OUT 0x0004 #define ETNA_SUBMIT_SOFTPIN 0x0008 -#define ETNA_SUBMIT_FLAGS \ - (ETNA_SUBMIT_NO_IMPLICIT | ETNA_SUBMIT_FENCE_FD_IN | \ - ETNA_SUBMIT_FENCE_FD_OUT | ETNA_SUBMIT_SOFTPIN) +#define ETNA_SUBMIT_FLAGS \ + (ETNA_SUBMIT_NO_IMPLICIT | ETNA_SUBMIT_FENCE_FD_IN | ETNA_SUBMIT_FENCE_FD_OUT | ETNA_SUBMIT_SOFTPIN) #define ETNA_PIPE_3D 0x00 #define ETNA_PIPE_2D 0x01 #define ETNA_PIPE_VG 0x02 @@ -280,39 +279,22 @@ struct drm_etnaviv_pm_signal { #define DRM_ETNAVIV_PM_QUERY_SIG 0x0b #define DRM_ETNAVIV_NUM_IOCTLS 0x0c -#define DRM_IOCTL_ETNAVIV_GET_PARAM \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, \ - struct drm_etnaviv_param) -#define DRM_IOCTL_ETNAVIV_GEM_NEW \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, \ - struct drm_etnaviv_gem_new) -#define DRM_IOCTL_ETNAVIV_GEM_INFO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, \ - struct drm_etnaviv_gem_info) -#define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP \ - DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, \ - struct drm_etnaviv_gem_cpu_prep) -#define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI \ - DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, \ - struct drm_etnaviv_gem_cpu_fini) -#define DRM_IOCTL_ETNAVIV_GEM_SUBMIT \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, \ - struct drm_etnaviv_gem_submit) -#define DRM_IOCTL_ETNAVIV_WAIT_FENCE \ - DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, \ - struct drm_etnaviv_wait_fence) -#define DRM_IOCTL_ETNAVIV_GEM_USERPTR \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, \ - struct drm_etnaviv_gem_userptr) -#define DRM_IOCTL_ETNAVIV_GEM_WAIT \ - DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, \ - struct drm_etnaviv_gem_wait) -#define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, \ - struct drm_etnaviv_pm_domain) -#define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, \ - struct drm_etnaviv_pm_signal) +#define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param) +#define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new) +#define DRM_IOCTL_ETNAVIV_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info) +#define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP \ + DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep) +#define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI \ + DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini) +#define DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit) +#define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence) +#define DRM_IOCTL_ETNAVIV_GEM_USERPTR \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr) +#define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait) +#define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain) +#define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal) #if defined(__cplusplus) } diff --git a/include/arch/x86_64/drm/exynos_drm.h b/include/arch/x86_64/drm/exynos_drm.h index 414cabdc..877f666b 100644 --- a/include/arch/x86_64/drm/exynos_drm.h +++ b/include/arch/x86_64/drm/exynos_drm.h @@ -324,9 +324,7 @@ enum drm_exynos_ipp_flag { DRM_EXYNOS_IPP_FLAG_NONBLOCK = 0x04, }; -#define DRM_EXYNOS_IPP_FLAGS \ - (DRM_EXYNOS_IPP_FLAG_EVENT | DRM_EXYNOS_IPP_FLAG_TEST_ONLY | \ - DRM_EXYNOS_IPP_FLAG_NONBLOCK) +#define DRM_EXYNOS_IPP_FLAGS (DRM_EXYNOS_IPP_FLAG_EVENT | DRM_EXYNOS_IPP_FLAG_TEST_ONLY | DRM_EXYNOS_IPP_FLAG_NONBLOCK) /** * Perform image processing described by array of drm_exynos_ipp_task_* @@ -366,42 +364,26 @@ struct drm_exynos_ioctl_ipp_commit { #define DRM_EXYNOS_IPP_GET_LIMITS 0x42 #define DRM_EXYNOS_IPP_COMMIT 0x43 -#define DRM_IOCTL_EXYNOS_GEM_CREATE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_CREATE, \ - struct drm_exynos_gem_create) -#define DRM_IOCTL_EXYNOS_GEM_MAP \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_MAP, \ - struct drm_exynos_gem_map) -#define DRM_IOCTL_EXYNOS_GEM_GET \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_GET, \ - struct drm_exynos_gem_info) - -#define DRM_IOCTL_EXYNOS_VIDI_CONNECTION \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_VIDI_CONNECTION, \ - struct drm_exynos_vidi_connection) - -#define DRM_IOCTL_EXYNOS_G2D_GET_VER \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_GET_VER, \ - struct drm_exynos_g2d_get_ver) -#define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_SET_CMDLIST, \ - struct drm_exynos_g2d_set_cmdlist) -#define DRM_IOCTL_EXYNOS_G2D_EXEC \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_EXEC, \ - struct drm_exynos_g2d_exec) - -#define DRM_IOCTL_EXYNOS_IPP_GET_RESOURCES \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_RESOURCES, \ - struct drm_exynos_ioctl_ipp_get_res) -#define DRM_IOCTL_EXYNOS_IPP_GET_CAPS \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_CAPS, \ - struct drm_exynos_ioctl_ipp_get_caps) -#define DRM_IOCTL_EXYNOS_IPP_GET_LIMITS \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_LIMITS, \ - struct drm_exynos_ioctl_ipp_get_limits) -#define DRM_IOCTL_EXYNOS_IPP_COMMIT \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_COMMIT, \ - struct drm_exynos_ioctl_ipp_commit) +#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create) +#define DRM_IOCTL_EXYNOS_GEM_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_MAP, struct drm_exynos_gem_map) +#define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info) + +#define DRM_IOCTL_EXYNOS_VIDI_CONNECTION \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection) + +#define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver) +#define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist) +#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec) + +#define DRM_IOCTL_EXYNOS_IPP_GET_RESOURCES \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_RESOURCES, struct drm_exynos_ioctl_ipp_get_res) +#define DRM_IOCTL_EXYNOS_IPP_GET_CAPS \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_CAPS, struct drm_exynos_ioctl_ipp_get_caps) +#define DRM_IOCTL_EXYNOS_IPP_GET_LIMITS \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_LIMITS, struct drm_exynos_ioctl_ipp_get_limits) +#define DRM_IOCTL_EXYNOS_IPP_COMMIT \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_COMMIT, struct drm_exynos_ioctl_ipp_commit) /* Exynos specific events */ #define DRM_EXYNOS_G2D_EVENT 0x80000000 diff --git a/include/arch/x86_64/drm/habanalabs_accel.h b/include/arch/x86_64/drm/habanalabs_accel.h index 60b1f21d..dd83a435 100644 --- a/include/arch/x86_64/drm/habanalabs_accel.h +++ b/include/arch/x86_64/drm/habanalabs_accel.h @@ -1008,11 +1008,7 @@ struct hl_info_pci_counters { __u64 replay_cnt; }; -enum hl_clk_throttling_type { - HL_CLK_THROTTLE_TYPE_POWER, - HL_CLK_THROTTLE_TYPE_THERMAL, - HL_CLK_THROTTLE_TYPE_MAX -}; +enum hl_clk_throttling_type { HL_CLK_THROTTLE_TYPE_POWER, HL_CLK_THROTTLE_TYPE_THERMAL, HL_CLK_THROTTLE_TYPE_MAX }; /* clk_throttling_reason masks */ #define HL_CLK_THROTTLE_POWER (1 << HL_CLK_THROTTLE_TYPE_POWER) @@ -1348,12 +1344,7 @@ struct hl_user_mapping { __u64 size; }; -enum gaudi_dcores { - HL_GAUDI_WS_DCORE, - HL_GAUDI_WN_DCORE, - HL_GAUDI_EN_DCORE, - HL_GAUDI_ES_DCORE -}; +enum gaudi_dcores { HL_GAUDI_WS_DCORE, HL_GAUDI_WN_DCORE, HL_GAUDI_EN_DCORE, HL_GAUDI_ES_DCORE }; /** * struct hl_info_args - Main structure to retrieve device related information. @@ -2237,8 +2228,7 @@ struct hl_debug_args { * definitions of structures in kernel and userspace, e.g. in case of old * userspace and new kernel driver */ -#define DRM_IOCTL_HL_INFO \ - DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_INFO, struct hl_info_args) +#define DRM_IOCTL_HL_INFO DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_INFO, struct hl_info_args) /* * Command Buffer @@ -2259,8 +2249,7 @@ struct hl_debug_args { * and won't be returned to user. * */ -#define DRM_IOCTL_HL_CB \ - DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_CB, union hl_cb_args) +#define DRM_IOCTL_HL_CB DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_CB, union hl_cb_args) /* * Command Submission @@ -2312,8 +2301,7 @@ struct hl_debug_args { * and only if CS N and CS N-1 are exactly the same (same CBs for the same * queues). */ -#define DRM_IOCTL_HL_CS \ - DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_CS, union hl_cs_args) +#define DRM_IOCTL_HL_CS DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_CS, union hl_cs_args) /* * Wait for Command Submission @@ -2345,8 +2333,7 @@ struct hl_debug_args { * HL_WAIT_CS_STATUS_ABORTED - The CS was aborted, usually because the * device was reset (EIO) */ -#define DRM_IOCTL_HL_WAIT_CS \ - DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_WAIT_CS, union hl_wait_cs_args) +#define DRM_IOCTL_HL_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_WAIT_CS, union hl_wait_cs_args) /* * Memory @@ -2363,8 +2350,7 @@ struct hl_debug_args { * There is an option for the user to specify the requested virtual address. * */ -#define DRM_IOCTL_HL_MEMORY \ - DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_MEMORY, union hl_mem_args) +#define DRM_IOCTL_HL_MEMORY DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_MEMORY, union hl_mem_args) /* * Debug @@ -2390,8 +2376,7 @@ struct hl_debug_args { * The driver can decide to "kick out" the user if he abuses this interface. * */ -#define DRM_IOCTL_HL_DEBUG \ - DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_DEBUG, struct hl_debug_args) +#define DRM_IOCTL_HL_DEBUG DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_DEBUG, struct hl_debug_args) #define HL_COMMAND_START (DRM_COMMAND_BASE + HL_IOCTL_INFO) #define HL_COMMAND_END (DRM_COMMAND_BASE + HL_IOCTL_DEBUG + 1) diff --git a/include/arch/x86_64/drm/i915_drm.h b/include/arch/x86_64/drm/i915_drm.h index e0403cb6..e9458f90 100644 --- a/include/arch/x86_64/drm/i915_drm.h +++ b/include/arch/x86_64/drm/i915_drm.h @@ -254,39 +254,29 @@ struct i915_engine_class_instance { * */ -enum drm_i915_pmu_engine_sample { - I915_SAMPLE_BUSY = 0, - I915_SAMPLE_WAIT = 1, - I915_SAMPLE_SEMA = 2 -}; +enum drm_i915_pmu_engine_sample { I915_SAMPLE_BUSY = 0, I915_SAMPLE_WAIT = 1, I915_SAMPLE_SEMA = 2 }; #define I915_PMU_SAMPLE_BITS (4) #define I915_PMU_SAMPLE_MASK (0xf) #define I915_PMU_SAMPLE_INSTANCE_BITS (8) -#define I915_PMU_CLASS_SHIFT \ - (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS) +#define I915_PMU_CLASS_SHIFT (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS) #define __I915_PMU_ENGINE(class, instance, sample) \ - ((class) << I915_PMU_CLASS_SHIFT | \ - (instance) << I915_PMU_SAMPLE_BITS | (sample)) + ((class) << I915_PMU_CLASS_SHIFT | (instance) << I915_PMU_SAMPLE_BITS | (sample)) -#define I915_PMU_ENGINE_BUSY(class, instance) \ - __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY) +#define I915_PMU_ENGINE_BUSY(class, instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY) -#define I915_PMU_ENGINE_WAIT(class, instance) \ - __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT) +#define I915_PMU_ENGINE_WAIT(class, instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT) -#define I915_PMU_ENGINE_SEMA(class, instance) \ - __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) +#define I915_PMU_ENGINE_SEMA(class, instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) /* * Top 4 bits of every non-engine counter are GT id. */ #define __I915_PMU_GT_SHIFT (60) -#define ___I915_PMU_OTHER(gt, x) \ - (((__u64)__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) | \ - ((__u64)(gt) << __I915_PMU_GT_SHIFT)) +#define ___I915_PMU_OTHER(gt, x) \ + (((__u64)__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) | ((__u64)(gt) << __I915_PMU_GT_SHIFT)) #define __I915_PMU_OTHER(x) ___I915_PMU_OTHER(0, x) @@ -312,11 +302,7 @@ enum drm_i915_pmu_engine_sample { #define I915_LOG_MIN_TEX_REGION_SIZE 14 typedef struct _drm_i915_init { - enum { - I915_INIT_DMA = 0x01, - I915_CLEANUP_DMA = 0x02, - I915_RESUME_DMA = 0x03 - } func; + enum { I915_INIT_DMA = 0x01, I915_CLEANUP_DMA = 0x02, I915_RESUME_DMA = 0x03 } func; unsigned int mmio_offset; int sarea_priv_offset; unsigned int ring_start; @@ -487,176 +473,100 @@ typedef struct _drm_i915_sarea { #define DRM_I915_GEM_CREATE_EXT 0x3c /* Must be kept compact -- no holes */ -#define DRM_IOCTL_I915_INIT \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) -#define DRM_IOCTL_I915_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLUSH) -#define DRM_IOCTL_I915_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLIP) -#define DRM_IOCTL_I915_BATCHBUFFER \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) -#define DRM_IOCTL_I915_IRQ_EMIT \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) -#define DRM_IOCTL_I915_IRQ_WAIT \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) -#define DRM_IOCTL_I915_GETPARAM \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) -#define DRM_IOCTL_I915_SETPARAM \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) -#define DRM_IOCTL_I915_ALLOC \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) -#define DRM_IOCTL_I915_FREE \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) -#define DRM_IOCTL_I915_INIT_HEAP \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) -#define DRM_IOCTL_I915_CMDBUFFER \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) -#define DRM_IOCTL_I915_DESTROY_HEAP \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, \ - drm_i915_mem_destroy_heap_t) -#define DRM_IOCTL_I915_SET_VBLANK_PIPE \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, \ - drm_i915_vblank_pipe_t) -#define DRM_IOCTL_I915_GET_VBLANK_PIPE \ - DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, \ - drm_i915_vblank_pipe_t) -#define DRM_IOCTL_I915_VBLANK_SWAP \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, \ - drm_i915_vblank_swap_t) -#define DRM_IOCTL_I915_HWS_ADDR \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) -#define DRM_IOCTL_I915_GEM_INIT \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) -#define DRM_IOCTL_I915_GEM_EXECBUFFER \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, \ - struct drm_i915_gem_execbuffer) -#define DRM_IOCTL_I915_GEM_EXECBUFFER2 \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, \ - struct drm_i915_gem_execbuffer2) -#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, \ - struct drm_i915_gem_execbuffer2) -#define DRM_IOCTL_I915_GEM_PIN \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) -#define DRM_IOCTL_I915_GEM_UNPIN \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, \ - struct drm_i915_gem_unpin) -#define DRM_IOCTL_I915_GEM_BUSY \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) -#define DRM_IOCTL_I915_GEM_SET_CACHING \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, \ - struct drm_i915_gem_caching) -#define DRM_IOCTL_I915_GEM_GET_CACHING \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, \ - struct drm_i915_gem_caching) -#define DRM_IOCTL_I915_GEM_THROTTLE \ - DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) -#define DRM_IOCTL_I915_GEM_ENTERVT \ - DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) -#define DRM_IOCTL_I915_GEM_LEAVEVT \ - DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) -#define DRM_IOCTL_I915_GEM_CREATE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, \ - struct drm_i915_gem_create) -#define DRM_IOCTL_I915_GEM_CREATE_EXT \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, \ - struct drm_i915_gem_create_ext) -#define DRM_IOCTL_I915_GEM_PREAD \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, \ - struct drm_i915_gem_pread) -#define DRM_IOCTL_I915_GEM_PWRITE \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, \ - struct drm_i915_gem_pwrite) -#define DRM_IOCTL_I915_GEM_MMAP \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) -#define DRM_IOCTL_I915_GEM_MMAP_GTT \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, \ - struct drm_i915_gem_mmap_gtt) -#define DRM_IOCTL_I915_GEM_MMAP_OFFSET \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, \ - struct drm_i915_gem_mmap_offset) -#define DRM_IOCTL_I915_GEM_SET_DOMAIN \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, \ - struct drm_i915_gem_set_domain) -#define DRM_IOCTL_I915_GEM_SW_FINISH \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, \ - struct drm_i915_gem_sw_finish) -#define DRM_IOCTL_I915_GEM_SET_TILING \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, \ - struct drm_i915_gem_set_tiling) -#define DRM_IOCTL_I915_GEM_GET_TILING \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, \ - struct drm_i915_gem_get_tiling) -#define DRM_IOCTL_I915_GEM_GET_APERTURE \ - DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, \ - struct drm_i915_gem_get_aperture) -#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, \ - struct drm_i915_get_pipe_from_crtc_id) -#define DRM_IOCTL_I915_GEM_MADVISE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, \ - struct drm_i915_gem_madvise) -#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, \ - struct drm_intel_overlay_put_image) -#define DRM_IOCTL_I915_OVERLAY_ATTRS \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, \ - struct drm_intel_overlay_attrs) -#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, \ - struct drm_intel_sprite_colorkey) -#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, \ - struct drm_intel_sprite_colorkey) -#define DRM_IOCTL_I915_GEM_WAIT \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) -#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, \ - struct drm_i915_gem_context_create) -#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, \ - struct drm_i915_gem_context_create_ext) -#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, \ - struct drm_i915_gem_context_destroy) -#define DRM_IOCTL_I915_REG_READ \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) -#define DRM_IOCTL_I915_GET_RESET_STATS \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, \ - struct drm_i915_reset_stats) -#define DRM_IOCTL_I915_GEM_USERPTR \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, \ - struct drm_i915_gem_userptr) -#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, \ - struct drm_i915_gem_context_param) -#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, \ - struct drm_i915_gem_context_param) -#define DRM_IOCTL_I915_PERF_OPEN \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, \ - struct drm_i915_perf_open_param) -#define DRM_IOCTL_I915_PERF_ADD_CONFIG \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, \ - struct drm_i915_perf_oa_config) -#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) -#define DRM_IOCTL_I915_QUERY \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query) -#define DRM_IOCTL_I915_GEM_VM_CREATE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, \ - struct drm_i915_gem_vm_control) -#define DRM_IOCTL_I915_GEM_VM_DESTROY \ - DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, \ - struct drm_i915_gem_vm_control) +#define DRM_IOCTL_I915_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) +#define DRM_IOCTL_I915_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLUSH) +#define DRM_IOCTL_I915_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLIP) +#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) +#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) +#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) +#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) +#define DRM_IOCTL_I915_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) +#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) +#define DRM_IOCTL_I915_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) +#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) +#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) +#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) +#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) +#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) +#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) +#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) +#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) +#define DRM_IOCTL_I915_GEM_EXECBUFFER \ + DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) +#define DRM_IOCTL_I915_GEM_EXECBUFFER2 \ + DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) +#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) +#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) +#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) +#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) +#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) +#define DRM_IOCTL_I915_GEM_GET_CACHING \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) +#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) +#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) +#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) +#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) +#define DRM_IOCTL_I915_GEM_CREATE_EXT \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext) +#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) +#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) +#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) +#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) +#define DRM_IOCTL_I915_GEM_MMAP_OFFSET \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset) +#define DRM_IOCTL_I915_GEM_SET_DOMAIN \ + DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) +#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) +#define DRM_IOCTL_I915_GEM_SET_TILING \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) +#define DRM_IOCTL_I915_GEM_GET_TILING \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) +#define DRM_IOCTL_I915_GEM_GET_APERTURE \ + DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) +#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) +#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) +#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE \ + DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) +#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) +#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) +#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) +#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) +#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) +#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext) +#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY \ + DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) +#define DRM_IOCTL_I915_REG_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) +#define DRM_IOCTL_I915_GET_RESET_STATS \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) +#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) +#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) +#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) +#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) +#define DRM_IOCTL_I915_PERF_ADD_CONFIG \ + DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) +#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) +#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query) +#define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control) +#define DRM_IOCTL_I915_GEM_VM_DESTROY \ + DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control) /* Allow drivers to submit batchbuffers directly to hardware, relying * on the security mechanisms provided by hardware. */ typedef struct drm_i915_batchbuffer { - int start; /* agp offset */ - int used; /* nr bytes in use */ - int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ - int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ - int num_cliprects; /* mulitpass with multiple cliprects? */ + int start; /* agp offset */ + int used; /* nr bytes in use */ + int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ + int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ + int num_cliprects; /* mulitpass with multiple cliprects? */ struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ } drm_i915_batchbuffer_t; @@ -664,11 +574,11 @@ typedef struct drm_i915_batchbuffer { * validated by the kernel prior to sending to hardware. */ typedef struct _drm_i915_cmdbuffer { - char *buf; /* pointer to userspace command buffer */ - int sz; /* nr bytes in buf */ - int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ - int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ - int num_cliprects; /* mulitpass with multiple cliprects? */ + char *buf; /* pointer to userspace command buffer */ + int sz; /* nr bytes in buf */ + int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ + int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ + int num_cliprects; /* mulitpass with multiple cliprects? */ struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */ } drm_i915_cmdbuffer_t; @@ -1669,11 +1579,9 @@ struct drm_i915_gem_execbuffer2 { __u64 rsvd2; }; -#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) -#define i915_execbuffer2_set_context_id(eb2, context) \ - (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK -#define i915_execbuffer2_get_context_id(eb2) \ - ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) +#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) +#define i915_execbuffer2_set_context_id(eb2, context) (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK +#define i915_execbuffer2_get_context_id(eb2) ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) struct drm_i915_gem_pin { /** Handle of the buffer to be pinned. */ @@ -2071,8 +1979,7 @@ struct drm_i915_gem_context_create_ext { __u32 flags; #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0) #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1) -#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \ - (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1)) +#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1)) /** * @extensions: Zero-terminated chain of extensions. @@ -2115,10 +2022,10 @@ struct drm_i915_gem_context_param { #define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */ #define I915_CONTEXT_DEFAULT_PRIORITY 0 #define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */ - /* - * When using the following param, value should be a pointer to - * drm_i915_gem_context_param_sseu. - */ + /* + * When using the following param, value should be a pointer to + * drm_i915_gem_context_param_sseu. + */ #define I915_CONTEXT_PARAM_SSEU 0x7 /* @@ -2671,12 +2578,10 @@ struct i915_context_engines_parallel_submit { */ struct i915_context_param_engines { - __u64 extensions; /* linked chain of extension blocks, 0 terminates */ -#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE \ - 0 /* see i915_context_engines_load_balance */ -#define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */ -#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT \ - 2 /* see i915_context_engines_parallel_submit */ + __u64 extensions; /* linked chain of extension blocks, 0 terminates */ +#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */ +#define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */ +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */ struct i915_engine_class_instance engines[]; } __attribute__((packed)); diff --git a/include/arch/x86_64/drm/ivpu_accel.h b/include/arch/x86_64/drm/ivpu_accel.h index 1198ec64..09304d80 100644 --- a/include/arch/x86_64/drm/ivpu_accel.h +++ b/include/arch/x86_64/drm/ivpu_accel.h @@ -26,52 +26,35 @@ extern "C" { #define DRM_IVPU_CMDQ_DESTROY 0x0c #define DRM_IVPU_CMDQ_SUBMIT 0x0d -#define DRM_IOCTL_IVPU_GET_PARAM \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_GET_PARAM, struct drm_ivpu_param) +#define DRM_IOCTL_IVPU_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_GET_PARAM, struct drm_ivpu_param) -#define DRM_IOCTL_IVPU_SET_PARAM \ - DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SET_PARAM, struct drm_ivpu_param) +#define DRM_IOCTL_IVPU_SET_PARAM DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SET_PARAM, struct drm_ivpu_param) -#define DRM_IOCTL_IVPU_BO_CREATE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_CREATE, \ - struct drm_ivpu_bo_create) +#define DRM_IOCTL_IVPU_BO_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_CREATE, struct drm_ivpu_bo_create) -#define DRM_IOCTL_IVPU_BO_INFO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_INFO, struct drm_ivpu_bo_info) +#define DRM_IOCTL_IVPU_BO_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_INFO, struct drm_ivpu_bo_info) -#define DRM_IOCTL_IVPU_SUBMIT \ - DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SUBMIT, struct drm_ivpu_submit) +#define DRM_IOCTL_IVPU_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SUBMIT, struct drm_ivpu_submit) -#define DRM_IOCTL_IVPU_BO_WAIT \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_WAIT, struct drm_ivpu_bo_wait) +#define DRM_IOCTL_IVPU_BO_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_WAIT, struct drm_ivpu_bo_wait) -#define DRM_IOCTL_IVPU_METRIC_STREAMER_START \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_START, \ - struct drm_ivpu_metric_streamer_start) +#define DRM_IOCTL_IVPU_METRIC_STREAMER_START \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_START, struct drm_ivpu_metric_streamer_start) -#define DRM_IOCTL_IVPU_METRIC_STREAMER_STOP \ - DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_STOP, \ - struct drm_ivpu_metric_streamer_stop) +#define DRM_IOCTL_IVPU_METRIC_STREAMER_STOP \ + DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_STOP, struct drm_ivpu_metric_streamer_stop) -#define DRM_IOCTL_IVPU_METRIC_STREAMER_GET_DATA \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_GET_DATA, \ - struct drm_ivpu_metric_streamer_get_data) +#define DRM_IOCTL_IVPU_METRIC_STREAMER_GET_DATA \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_GET_DATA, struct drm_ivpu_metric_streamer_get_data) -#define DRM_IOCTL_IVPU_METRIC_STREAMER_GET_INFO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_GET_INFO, \ - struct drm_ivpu_metric_streamer_get_data) +#define DRM_IOCTL_IVPU_METRIC_STREAMER_GET_INFO \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_GET_INFO, struct drm_ivpu_metric_streamer_get_data) -#define DRM_IOCTL_IVPU_CMDQ_CREATE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_CMDQ_CREATE, \ - struct drm_ivpu_cmdq_create) +#define DRM_IOCTL_IVPU_CMDQ_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_CMDQ_CREATE, struct drm_ivpu_cmdq_create) -#define DRM_IOCTL_IVPU_CMDQ_DESTROY \ - DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_CMDQ_DESTROY, \ - struct drm_ivpu_cmdq_destroy) +#define DRM_IOCTL_IVPU_CMDQ_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_CMDQ_DESTROY, struct drm_ivpu_cmdq_destroy) -#define DRM_IOCTL_IVPU_CMDQ_SUBMIT \ - DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_CMDQ_SUBMIT, \ - struct drm_ivpu_cmdq_submit) +#define DRM_IOCTL_IVPU_CMDQ_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_CMDQ_SUBMIT, struct drm_ivpu_cmdq_submit) /** * DOC: contexts @@ -202,9 +185,7 @@ struct drm_ivpu_param { #define DRM_IVPU_BO_WC 0x00020000 #define DRM_IVPU_BO_CACHE_MASK 0x00030000 -#define DRM_IVPU_BO_FLAGS \ - (DRM_IVPU_BO_HIGH_MEM | DRM_IVPU_BO_MAPPABLE | DRM_IVPU_BO_DMA_MEM | \ - DRM_IVPU_BO_CACHE_MASK) +#define DRM_IVPU_BO_FLAGS (DRM_IVPU_BO_HIGH_MEM | DRM_IVPU_BO_MAPPABLE | DRM_IVPU_BO_DMA_MEM | DRM_IVPU_BO_CACHE_MASK) /** * struct drm_ivpu_bo_create - Create BO backed by SHMEM diff --git a/include/arch/x86_64/drm/lima_drm.h b/include/arch/x86_64/drm/lima_drm.h index 92917b4c..c22c636d 100644 --- a/include/arch/x86_64/drm/lima_drm.h +++ b/include/arch/x86_64/drm/lima_drm.h @@ -121,8 +121,8 @@ struct drm_lima_gem_submit { __u64 bos; /* in, array of drm_lima_gem_submit_bo */ __u64 frame; /* in, GP/PP frame */ __u32 flags; /* in, submit flags */ - __u32 out_sync; /* in, drm_syncobj handle used to wait task finish after - submission */ + __u32 out_sync; /* in, drm_syncobj handle used to wait task finish after + submission */ __u32 in_sync[2]; /* in, drm_syncobj handle used to wait before start this task */ }; @@ -163,24 +163,13 @@ struct drm_lima_ctx_free { #define DRM_LIMA_CTX_CREATE 0x05 #define DRM_LIMA_CTX_FREE 0x06 -#define DRM_IOCTL_LIMA_GET_PARAM \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GET_PARAM, \ - struct drm_lima_get_param) -#define DRM_IOCTL_LIMA_GEM_CREATE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_CREATE, \ - struct drm_lima_gem_create) -#define DRM_IOCTL_LIMA_GEM_INFO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_INFO, struct drm_lima_gem_info) -#define DRM_IOCTL_LIMA_GEM_SUBMIT \ - DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_SUBMIT, \ - struct drm_lima_gem_submit) -#define DRM_IOCTL_LIMA_GEM_WAIT \ - DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_WAIT, struct drm_lima_gem_wait) -#define DRM_IOCTL_LIMA_CTX_CREATE \ - DRM_IOR(DRM_COMMAND_BASE + DRM_LIMA_CTX_CREATE, \ - struct drm_lima_ctx_create) -#define DRM_IOCTL_LIMA_CTX_FREE \ - DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_CTX_FREE, struct drm_lima_ctx_free) +#define DRM_IOCTL_LIMA_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GET_PARAM, struct drm_lima_get_param) +#define DRM_IOCTL_LIMA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_CREATE, struct drm_lima_gem_create) +#define DRM_IOCTL_LIMA_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_INFO, struct drm_lima_gem_info) +#define DRM_IOCTL_LIMA_GEM_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_SUBMIT, struct drm_lima_gem_submit) +#define DRM_IOCTL_LIMA_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_WAIT, struct drm_lima_gem_wait) +#define DRM_IOCTL_LIMA_CTX_CREATE DRM_IOR(DRM_COMMAND_BASE + DRM_LIMA_CTX_CREATE, struct drm_lima_ctx_create) +#define DRM_IOCTL_LIMA_CTX_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_CTX_FREE, struct drm_lima_ctx_free) #if defined(__cplusplus) } diff --git a/include/arch/x86_64/drm/msm_drm.h b/include/arch/x86_64/drm/msm_drm.h index efc01123..caeac45d 100644 --- a/include/arch/x86_64/drm/msm_drm.h +++ b/include/arch/x86_64/drm/msm_drm.h @@ -71,18 +71,17 @@ struct drm_msm_timespec { * "RW" indicates a param that can be both read (GET_PARAM) and written * (SET_PARAM) */ -#define MSM_PARAM_GPU_ID 0x01 /* RO */ -#define MSM_PARAM_GMEM_SIZE 0x02 /* RO */ -#define MSM_PARAM_CHIP_ID 0x03 /* RO */ -#define MSM_PARAM_MAX_FREQ 0x04 /* RO */ -#define MSM_PARAM_TIMESTAMP 0x05 /* RO */ -#define MSM_PARAM_GMEM_BASE 0x06 /* RO */ -#define MSM_PARAM_PRIORITIES 0x07 /* RO: The # of priority levels */ -#define MSM_PARAM_PP_PGTABLE 0x08 /* RO: Deprecated, always returns zero */ -#define MSM_PARAM_FAULTS 0x09 /* RO */ -#define MSM_PARAM_SUSPENDS 0x0a /* RO */ -#define MSM_PARAM_SYSPROF \ - 0x0b /* WO: 1 preserves perfcntrs, 2 also disables suspend */ +#define MSM_PARAM_GPU_ID 0x01 /* RO */ +#define MSM_PARAM_GMEM_SIZE 0x02 /* RO */ +#define MSM_PARAM_CHIP_ID 0x03 /* RO */ +#define MSM_PARAM_MAX_FREQ 0x04 /* RO */ +#define MSM_PARAM_TIMESTAMP 0x05 /* RO */ +#define MSM_PARAM_GMEM_BASE 0x06 /* RO */ +#define MSM_PARAM_PRIORITIES 0x07 /* RO: The # of priority levels */ +#define MSM_PARAM_PP_PGTABLE 0x08 /* RO: Deprecated, always returns zero */ +#define MSM_PARAM_FAULTS 0x09 /* RO */ +#define MSM_PARAM_SUSPENDS 0x0a /* RO */ +#define MSM_PARAM_SYSPROF 0x0b /* WO: 1 preserves perfcntrs, 2 also disables suspend */ #define MSM_PARAM_COMM 0x0c /* WO: override for task->comm */ #define MSM_PARAM_CMDLINE 0x0d /* WO: override for task cmdline */ #define MSM_PARAM_VA_START 0x0e /* RO: start of valid GPU iova range */ @@ -161,9 +160,7 @@ struct drm_msm_param { #define MSM_BO_UNCACHED 0x00040000 /* deprecated, use MSM_BO_WC */ #define MSM_BO_CACHED_COHERENT 0x080000 -#define MSM_BO_FLAGS \ - (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_NO_SHARE | \ - MSM_BO_CACHE_MASK) +#define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_NO_SHARE | MSM_BO_CACHE_MASK) struct drm_msm_gem_new { __u64 size; /* in */ @@ -200,8 +197,7 @@ struct drm_msm_gem_info { #define MSM_PREP_NOSYNC 0x04 #define MSM_PREP_BOOST 0x08 -#define MSM_PREP_FLAGS \ - (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC | MSM_PREP_BOOST | 0) +#define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC | MSM_PREP_BOOST | 0) struct drm_msm_gem_cpu_prep { __u32 handle; /* in */ @@ -289,9 +285,7 @@ struct drm_msm_gem_submit_cmd { #define MSM_SUBMIT_BO_DUMP 0x0004 #define MSM_SUBMIT_BO_NO_IMPLICIT 0x0008 -#define MSM_SUBMIT_BO_FLAGS \ - (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE | MSM_SUBMIT_BO_DUMP | \ - MSM_SUBMIT_BO_NO_IMPLICIT) +#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE | MSM_SUBMIT_BO_DUMP | MSM_SUBMIT_BO_NO_IMPLICIT) struct drm_msm_gem_submit_bo { __u32 flags; /* in, mask of MSM_SUBMIT_BO_x */ @@ -309,24 +303,23 @@ struct drm_msm_gem_submit_bo { #define MSM_SUBMIT_FENCE_SN_IN \ 0x02000000 /* userspace passes in seqno fence \ */ -#define MSM_SUBMIT_FLAGS \ - (MSM_SUBMIT_NO_IMPLICIT | MSM_SUBMIT_FENCE_FD_IN | \ - MSM_SUBMIT_FENCE_FD_OUT | MSM_SUBMIT_SUDO | MSM_SUBMIT_SYNCOBJ_IN | \ - MSM_SUBMIT_SYNCOBJ_OUT | MSM_SUBMIT_FENCE_SN_IN | 0) +#define MSM_SUBMIT_FLAGS \ + (MSM_SUBMIT_NO_IMPLICIT | MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_FENCE_FD_OUT | MSM_SUBMIT_SUDO | \ + MSM_SUBMIT_SYNCOBJ_IN | MSM_SUBMIT_SYNCOBJ_OUT | MSM_SUBMIT_FENCE_SN_IN | 0) /* Each cmdstream submit consists of a table of buffers involved, and * one or more cmdstream buffers. This allows for conditional execution * (context-restore), and IB buffers needed for per tile/bin draw cmds. */ struct drm_msm_gem_submit { - __u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */ - __u32 fence; /* out (or in with MSM_SUBMIT_FENCE_SN_IN flag) */ - __u32 nr_bos; /* in, number of submit_bo's */ - __u32 nr_cmds; /* in, number of submit_cmd's */ - __u64 bos; /* in, ptr to array of submit_bo's */ - __u64 cmds; /* in, ptr to array of submit_cmd's */ - __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */ - __u32 queueid; /* in, submitqueue id */ + __u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */ + __u32 fence; /* out (or in with MSM_SUBMIT_FENCE_SN_IN flag) */ + __u32 nr_bos; /* in, number of submit_bo's */ + __u32 nr_cmds; /* in, number of submit_cmd's */ + __u64 bos; /* in, ptr to array of submit_bo's */ + __u64 cmds; /* in, ptr to array of submit_cmd's */ + __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */ + __u32 queueid; /* in, submitqueue id */ __u64 in_syncobjs; /* in, ptr to array of drm_msm_syncobj */ __u64 out_syncobjs; /* in, ptr to array of drm_msm_syncobj */ __u32 nr_in_syncobjs; /* in, number of entries in in_syncobj */ @@ -364,8 +357,7 @@ struct drm_msm_vm_bind_op { #define MSM_VM_BIND_FENCE_FD_IN 0x00000001 #define MSM_VM_BIND_FENCE_FD_OUT 0x00000002 -#define MSM_VM_BIND_FLAGS \ - (MSM_VM_BIND_FENCE_FD_IN | MSM_VM_BIND_FENCE_FD_OUT | 0) +#define MSM_VM_BIND_FLAGS (MSM_VM_BIND_FENCE_FD_IN | MSM_VM_BIND_FENCE_FD_OUT | 0) /** * struct drm_msm_vm_bind - Input of &DRM_IOCTL_MSM_VM_BIND @@ -428,8 +420,7 @@ struct drm_msm_wait_fence { * In the WILLNEED case, 'retained' indicates to userspace whether the * backing pages still exist. */ -#define MSM_MADV_WILLNEED \ - 0 /* backing pages are needed, status returned in 'retained' */ +#define MSM_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */ #define MSM_MADV_DONTNEED 1 /* backing pages not needed */ #define __MSM_MADV_PURGED 2 /* internal state */ @@ -452,8 +443,7 @@ struct drm_msm_gem_madvise { #define MSM_SUBMITQUEUE_ALLOW_PREEMPT 0x00000001 #define MSM_SUBMITQUEUE_VM_BIND 0x00000002 /* virtual queue for VM_BIND ops */ -#define MSM_SUBMITQUEUE_FLAGS \ - (MSM_SUBMITQUEUE_ALLOW_PREEMPT | MSM_SUBMITQUEUE_VM_BIND | 0) +#define MSM_SUBMITQUEUE_FLAGS (MSM_SUBMITQUEUE_ALLOW_PREEMPT | MSM_SUBMITQUEUE_VM_BIND | 0) /* * The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1, @@ -492,39 +482,20 @@ struct drm_msm_submitqueue_query { #define DRM_MSM_SUBMITQUEUE_QUERY 0x0C #define DRM_MSM_VM_BIND 0x0D -#define DRM_IOCTL_MSM_GET_PARAM \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) -#define DRM_IOCTL_MSM_SET_PARAM \ - DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SET_PARAM, struct drm_msm_param) -#define DRM_IOCTL_MSM_GEM_NEW \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) -#define DRM_IOCTL_MSM_GEM_INFO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) -#define DRM_IOCTL_MSM_GEM_CPU_PREP \ - DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, \ - struct drm_msm_gem_cpu_prep) -#define DRM_IOCTL_MSM_GEM_CPU_FINI \ - DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, \ - struct drm_msm_gem_cpu_fini) -#define DRM_IOCTL_MSM_GEM_SUBMIT \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, \ - struct drm_msm_gem_submit) -#define DRM_IOCTL_MSM_WAIT_FENCE \ - DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, \ - struct drm_msm_wait_fence) -#define DRM_IOCTL_MSM_GEM_MADVISE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, \ - struct drm_msm_gem_madvise) -#define DRM_IOCTL_MSM_SUBMITQUEUE_NEW \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, \ - struct drm_msm_submitqueue) -#define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE \ - DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32) -#define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY \ - DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, \ - struct drm_msm_submitqueue_query) -#define DRM_IOCTL_MSM_VM_BIND \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_VM_BIND, struct drm_msm_vm_bind) +#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) +#define DRM_IOCTL_MSM_SET_PARAM DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SET_PARAM, struct drm_msm_param) +#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) +#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) +#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) +#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) +#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) +#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) +#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) +#define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue) +#define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32) +#define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY \ + DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query) +#define DRM_IOCTL_MSM_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_VM_BIND, struct drm_msm_vm_bind) #if defined(__cplusplus) } diff --git a/include/arch/x86_64/drm/nouveau_drm.h b/include/arch/x86_64/drm/nouveau_drm.h index 8ba0ee86..78659301 100644 --- a/include/arch/x86_64/drm/nouveau_drm.h +++ b/include/arch/x86_64/drm/nouveau_drm.h @@ -496,47 +496,27 @@ struct drm_nouveau_svm_bind { */ #define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31) -#define DRM_IOCTL_NOUVEAU_GETPARAM \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, \ - struct drm_nouveau_getparam) -#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, \ - struct drm_nouveau_channel_alloc) -#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE \ - DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, \ - struct drm_nouveau_channel_free) - -#define DRM_IOCTL_NOUVEAU_SVM_INIT \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, \ - struct drm_nouveau_svm_init) -#define DRM_IOCTL_NOUVEAU_SVM_BIND \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, \ - struct drm_nouveau_svm_bind) - -#define DRM_IOCTL_NOUVEAU_GEM_NEW \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, \ - struct drm_nouveau_gem_new) -#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, \ - struct drm_nouveau_gem_pushbuf) -#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP \ - DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, \ - struct drm_nouveau_gem_cpu_prep) -#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI \ - DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, \ - struct drm_nouveau_gem_cpu_fini) -#define DRM_IOCTL_NOUVEAU_GEM_INFO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, \ - struct drm_nouveau_gem_info) - -#define DRM_IOCTL_NOUVEAU_VM_INIT \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_INIT, \ - struct drm_nouveau_vm_init) -#define DRM_IOCTL_NOUVEAU_VM_BIND \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_BIND, \ - struct drm_nouveau_vm_bind) -#define DRM_IOCTL_NOUVEAU_EXEC \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_EXEC, struct drm_nouveau_exec) +#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam) +#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc) +#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE \ + DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free) + +#define DRM_IOCTL_NOUVEAU_SVM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init) +#define DRM_IOCTL_NOUVEAU_SVM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind) + +#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new) +#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf) +#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP \ + DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep) +#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI \ + DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) +#define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) + +#define DRM_IOCTL_NOUVEAU_VM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_INIT, struct drm_nouveau_vm_init) +#define DRM_IOCTL_NOUVEAU_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_BIND, struct drm_nouveau_vm_bind) +#define DRM_IOCTL_NOUVEAU_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_EXEC, struct drm_nouveau_exec) #if defined(__cplusplus) } #endif diff --git a/include/arch/x86_64/drm/nova_drm.h b/include/arch/x86_64/drm/nova_drm.h index 5725b84e..d29dfbb9 100644 --- a/include/arch/x86_64/drm/nova_drm.h +++ b/include/arch/x86_64/drm/nova_drm.h @@ -86,13 +86,9 @@ struct drm_nova_gem_info { /* Note: this is an enum so that it can be resolved by Rust bindgen. */ enum { - DRM_IOCTL_NOVA_GETPARAM = DRM_IOWR(DRM_COMMAND_BASE + DRM_NOVA_GETPARAM, - struct drm_nova_getparam), - DRM_IOCTL_NOVA_GEM_CREATE = - DRM_IOWR(DRM_COMMAND_BASE + DRM_NOVA_GEM_CREATE, - struct drm_nova_gem_create), - DRM_IOCTL_NOVA_GEM_INFO = DRM_IOWR(DRM_COMMAND_BASE + DRM_NOVA_GEM_INFO, - struct drm_nova_gem_info), + DRM_IOCTL_NOVA_GETPARAM = DRM_IOWR(DRM_COMMAND_BASE + DRM_NOVA_GETPARAM, struct drm_nova_getparam), + DRM_IOCTL_NOVA_GEM_CREATE = DRM_IOWR(DRM_COMMAND_BASE + DRM_NOVA_GEM_CREATE, struct drm_nova_gem_create), + DRM_IOCTL_NOVA_GEM_INFO = DRM_IOWR(DRM_COMMAND_BASE + DRM_NOVA_GEM_INFO, struct drm_nova_gem_info), }; #if defined(__cplusplus) diff --git a/include/arch/x86_64/drm/omap_drm.h b/include/arch/x86_64/drm/omap_drm.h index 54f01ad1..dbb3c58e 100644 --- a/include/arch/x86_64/drm/omap_drm.h +++ b/include/arch/x86_64/drm/omap_drm.h @@ -113,20 +113,12 @@ struct drm_omap_gem_info { #define DRM_OMAP_GEM_INFO 0x06 #define DRM_OMAP_NUM_IOCTLS 0x07 -#define DRM_IOCTL_OMAP_GET_PARAM \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GET_PARAM, struct drm_omap_param) -#define DRM_IOCTL_OMAP_SET_PARAM \ - DRM_IOW(DRM_COMMAND_BASE + DRM_OMAP_SET_PARAM, struct drm_omap_param) -#define DRM_IOCTL_OMAP_GEM_NEW \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GEM_NEW, struct drm_omap_gem_new) -#define DRM_IOCTL_OMAP_GEM_CPU_PREP \ - DRM_IOW(DRM_COMMAND_BASE + DRM_OMAP_GEM_CPU_PREP, \ - struct drm_omap_gem_cpu_prep) -#define DRM_IOCTL_OMAP_GEM_CPU_FINI \ - DRM_IOW(DRM_COMMAND_BASE + DRM_OMAP_GEM_CPU_FINI, \ - struct drm_omap_gem_cpu_fini) -#define DRM_IOCTL_OMAP_GEM_INFO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GEM_INFO, struct drm_omap_gem_info) +#define DRM_IOCTL_OMAP_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GET_PARAM, struct drm_omap_param) +#define DRM_IOCTL_OMAP_SET_PARAM DRM_IOW(DRM_COMMAND_BASE + DRM_OMAP_SET_PARAM, struct drm_omap_param) +#define DRM_IOCTL_OMAP_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GEM_NEW, struct drm_omap_gem_new) +#define DRM_IOCTL_OMAP_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_OMAP_GEM_CPU_PREP, struct drm_omap_gem_cpu_prep) +#define DRM_IOCTL_OMAP_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_OMAP_GEM_CPU_FINI, struct drm_omap_gem_cpu_fini) +#define DRM_IOCTL_OMAP_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GEM_INFO, struct drm_omap_gem_info) #if defined(__cplusplus) } diff --git a/include/arch/x86_64/drm/panfrost_drm.h b/include/arch/x86_64/drm/panfrost_drm.h index 2ce0e858..accbcba2 100644 --- a/include/arch/x86_64/drm/panfrost_drm.h +++ b/include/arch/x86_64/drm/panfrost_drm.h @@ -23,30 +23,16 @@ extern "C" { #define DRM_PANFROST_MADVISE 0x08 #define DRM_PANFROST_SET_LABEL_BO 0x09 -#define DRM_IOCTL_PANFROST_SUBMIT \ - DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_SUBMIT, \ - struct drm_panfrost_submit) -#define DRM_IOCTL_PANFROST_WAIT_BO \ - DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_WAIT_BO, \ - struct drm_panfrost_wait_bo) -#define DRM_IOCTL_PANFROST_CREATE_BO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_CREATE_BO, \ - struct drm_panfrost_create_bo) -#define DRM_IOCTL_PANFROST_MMAP_BO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_MMAP_BO, \ - struct drm_panfrost_mmap_bo) -#define DRM_IOCTL_PANFROST_GET_PARAM \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_PARAM, \ - struct drm_panfrost_get_param) -#define DRM_IOCTL_PANFROST_GET_BO_OFFSET \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_BO_OFFSET, \ - struct drm_panfrost_get_bo_offset) -#define DRM_IOCTL_PANFROST_MADVISE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_MADVISE, \ - struct drm_panfrost_madvise) -#define DRM_IOCTL_PANFROST_SET_LABEL_BO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_SET_LABEL_BO, \ - struct drm_panfrost_set_label_bo) +#define DRM_IOCTL_PANFROST_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_SUBMIT, struct drm_panfrost_submit) +#define DRM_IOCTL_PANFROST_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_WAIT_BO, struct drm_panfrost_wait_bo) +#define DRM_IOCTL_PANFROST_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_CREATE_BO, struct drm_panfrost_create_bo) +#define DRM_IOCTL_PANFROST_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_MMAP_BO, struct drm_panfrost_mmap_bo) +#define DRM_IOCTL_PANFROST_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_PARAM, struct drm_panfrost_get_param) +#define DRM_IOCTL_PANFROST_GET_BO_OFFSET \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_BO_OFFSET, struct drm_panfrost_get_bo_offset) +#define DRM_IOCTL_PANFROST_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_MADVISE, struct drm_panfrost_madvise) +#define DRM_IOCTL_PANFROST_SET_LABEL_BO \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_SET_LABEL_BO, struct drm_panfrost_set_label_bo) /* * Unstable ioctl(s): only exposed when the unsafe unstable_ioctls module @@ -54,12 +40,10 @@ extern "C" { * All these ioctl(s) are subject to deprecation, so please don't rely on * them for anything but debugging purpose. */ -#define DRM_IOCTL_PANFROST_PERFCNT_ENABLE \ - DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_PERFCNT_ENABLE, \ - struct drm_panfrost_perfcnt_enable) -#define DRM_IOCTL_PANFROST_PERFCNT_DUMP \ - DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_PERFCNT_DUMP, \ - struct drm_panfrost_perfcnt_dump) +#define DRM_IOCTL_PANFROST_PERFCNT_ENABLE \ + DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_PERFCNT_ENABLE, struct drm_panfrost_perfcnt_enable) +#define DRM_IOCTL_PANFROST_PERFCNT_DUMP \ + DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_PERFCNT_DUMP, struct drm_panfrost_perfcnt_dump) #define PANFROST_JD_REQ_FS (1 << 0) #define PANFROST_JD_REQ_CYCLE_COUNT (1 << 1) @@ -240,8 +224,7 @@ struct drm_panfrost_perfcnt_dump { * In the WILLNEED case, 'retained' indicates to userspace whether the * backing pages still exist. */ -#define PANFROST_MADV_WILLNEED \ - 0 /* backing pages are needed, status returned in 'retained' */ +#define PANFROST_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */ #define PANFROST_MADV_DONTNEED 1 /* backing pages not needed */ struct drm_panfrost_madvise { diff --git a/include/arch/x86_64/drm/panthor_drm.h b/include/arch/x86_64/drm/panthor_drm.h index cd9b3ad8..e5517d39 100644 --- a/include/arch/x86_64/drm/panthor_drm.h +++ b/include/arch/x86_64/drm/panthor_drm.h @@ -67,9 +67,8 @@ extern "C" { */ #define DRM_PANTHOR_USER_MMIO_OFFSET_32BIT (1ull << 43) #define DRM_PANTHOR_USER_MMIO_OFFSET_64BIT (1ull << 56) -#define DRM_PANTHOR_USER_MMIO_OFFSET \ - (sizeof(unsigned long) < 8 ? DRM_PANTHOR_USER_MMIO_OFFSET_32BIT : \ - DRM_PANTHOR_USER_MMIO_OFFSET_64BIT) +#define DRM_PANTHOR_USER_MMIO_OFFSET \ + (sizeof(unsigned long) < 8 ? DRM_PANTHOR_USER_MMIO_OFFSET_32BIT : DRM_PANTHOR_USER_MMIO_OFFSET_64BIT) #define DRM_PANTHOR_USER_FLUSH_ID_MMIO_OFFSET (DRM_PANTHOR_USER_MMIO_OFFSET | 0) /** @@ -184,10 +183,7 @@ struct drm_panthor_obj_array { * Macro initializing a drm_panthor_obj_array based on the object size as known * by userspace. */ -#define DRM_PANTHOR_OBJ_ARRAY(cnt, ptr) \ - { .stride = sizeof((ptr)[0]), \ - .count = (cnt), \ - .array = (__u64)(uintptr_t)(ptr) } +#define DRM_PANTHOR_OBJ_ARRAY(cnt, ptr) { .stride = sizeof((ptr)[0]), .count = (cnt), .array = (__u64)(uintptr_t)(ptr) } /** * enum drm_panthor_sync_op_flags - Synchronization operation flags. @@ -1097,40 +1093,25 @@ struct drm_panthor_set_user_mmio_offset { * * Return: An IOCTL number to be passed to ioctl() from userspace. */ -#define DRM_IOCTL_PANTHOR(__access, __id, __type) \ - DRM_IO##__access(DRM_COMMAND_BASE + DRM_PANTHOR_##__id, \ - struct drm_panthor_##__type) +#define DRM_IOCTL_PANTHOR(__access, __id, __type) \ + DRM_IO##__access(DRM_COMMAND_BASE + DRM_PANTHOR_##__id, struct drm_panthor_##__type) enum { - DRM_IOCTL_PANTHOR_DEV_QUERY = - DRM_IOCTL_PANTHOR(WR, DEV_QUERY, dev_query), - DRM_IOCTL_PANTHOR_VM_CREATE = - DRM_IOCTL_PANTHOR(WR, VM_CREATE, vm_create), - DRM_IOCTL_PANTHOR_VM_DESTROY = - DRM_IOCTL_PANTHOR(WR, VM_DESTROY, vm_destroy), + DRM_IOCTL_PANTHOR_DEV_QUERY = DRM_IOCTL_PANTHOR(WR, DEV_QUERY, dev_query), + DRM_IOCTL_PANTHOR_VM_CREATE = DRM_IOCTL_PANTHOR(WR, VM_CREATE, vm_create), + DRM_IOCTL_PANTHOR_VM_DESTROY = DRM_IOCTL_PANTHOR(WR, VM_DESTROY, vm_destroy), DRM_IOCTL_PANTHOR_VM_BIND = DRM_IOCTL_PANTHOR(WR, VM_BIND, vm_bind), - DRM_IOCTL_PANTHOR_VM_GET_STATE = - DRM_IOCTL_PANTHOR(WR, VM_GET_STATE, vm_get_state), - DRM_IOCTL_PANTHOR_BO_CREATE = - DRM_IOCTL_PANTHOR(WR, BO_CREATE, bo_create), - DRM_IOCTL_PANTHOR_BO_MMAP_OFFSET = - DRM_IOCTL_PANTHOR(WR, BO_MMAP_OFFSET, bo_mmap_offset), - DRM_IOCTL_PANTHOR_GROUP_CREATE = - DRM_IOCTL_PANTHOR(WR, GROUP_CREATE, group_create), - DRM_IOCTL_PANTHOR_GROUP_DESTROY = - DRM_IOCTL_PANTHOR(WR, GROUP_DESTROY, group_destroy), - DRM_IOCTL_PANTHOR_GROUP_SUBMIT = - DRM_IOCTL_PANTHOR(WR, GROUP_SUBMIT, group_submit), - DRM_IOCTL_PANTHOR_GROUP_GET_STATE = - DRM_IOCTL_PANTHOR(WR, GROUP_GET_STATE, group_get_state), - DRM_IOCTL_PANTHOR_TILER_HEAP_CREATE = - DRM_IOCTL_PANTHOR(WR, TILER_HEAP_CREATE, tiler_heap_create), - DRM_IOCTL_PANTHOR_TILER_HEAP_DESTROY = - DRM_IOCTL_PANTHOR(WR, TILER_HEAP_DESTROY, tiler_heap_destroy), - DRM_IOCTL_PANTHOR_BO_SET_LABEL = - DRM_IOCTL_PANTHOR(WR, BO_SET_LABEL, bo_set_label), - DRM_IOCTL_PANTHOR_SET_USER_MMIO_OFFSET = DRM_IOCTL_PANTHOR( - WR, SET_USER_MMIO_OFFSET, set_user_mmio_offset), + DRM_IOCTL_PANTHOR_VM_GET_STATE = DRM_IOCTL_PANTHOR(WR, VM_GET_STATE, vm_get_state), + DRM_IOCTL_PANTHOR_BO_CREATE = DRM_IOCTL_PANTHOR(WR, BO_CREATE, bo_create), + DRM_IOCTL_PANTHOR_BO_MMAP_OFFSET = DRM_IOCTL_PANTHOR(WR, BO_MMAP_OFFSET, bo_mmap_offset), + DRM_IOCTL_PANTHOR_GROUP_CREATE = DRM_IOCTL_PANTHOR(WR, GROUP_CREATE, group_create), + DRM_IOCTL_PANTHOR_GROUP_DESTROY = DRM_IOCTL_PANTHOR(WR, GROUP_DESTROY, group_destroy), + DRM_IOCTL_PANTHOR_GROUP_SUBMIT = DRM_IOCTL_PANTHOR(WR, GROUP_SUBMIT, group_submit), + DRM_IOCTL_PANTHOR_GROUP_GET_STATE = DRM_IOCTL_PANTHOR(WR, GROUP_GET_STATE, group_get_state), + DRM_IOCTL_PANTHOR_TILER_HEAP_CREATE = DRM_IOCTL_PANTHOR(WR, TILER_HEAP_CREATE, tiler_heap_create), + DRM_IOCTL_PANTHOR_TILER_HEAP_DESTROY = DRM_IOCTL_PANTHOR(WR, TILER_HEAP_DESTROY, tiler_heap_destroy), + DRM_IOCTL_PANTHOR_BO_SET_LABEL = DRM_IOCTL_PANTHOR(WR, BO_SET_LABEL, bo_set_label), + DRM_IOCTL_PANTHOR_SET_USER_MMIO_OFFSET = DRM_IOCTL_PANTHOR(WR, SET_USER_MMIO_OFFSET, set_user_mmio_offset), }; #if defined(__cplusplus) diff --git a/include/arch/x86_64/drm/pvr_drm.h b/include/arch/x86_64/drm/pvr_drm.h index fdaac8dd..b77a84fe 100644 --- a/include/arch/x86_64/drm/pvr_drm.h +++ b/include/arch/x86_64/drm/pvr_drm.h @@ -71,10 +71,7 @@ struct drm_pvr_obj_array { * * Return: Literal of type &struct drm_pvr_obj_array. */ -#define DRM_PVR_OBJ_ARRAY(cnt, ptr) \ - { .stride = sizeof((ptr)[0]), \ - .count = (cnt), \ - .array = (__u64)(uintptr_t)(ptr) } +#define DRM_PVR_OBJ_ARRAY(cnt, ptr) { .stride = sizeof((ptr)[0]), .count = (cnt), .array = (__u64)(uintptr_t)(ptr) } /** * DOC: PowerVR IOCTL interface @@ -94,30 +91,22 @@ struct drm_pvr_obj_array { * * Return: An IOCTL number to be passed to ioctl() from userspace. */ -#define PVR_IOCTL(_ioctl, _mode, _data) \ - _mode(DRM_COMMAND_BASE + (_ioctl), struct drm_pvr_ioctl_##_data##_args) - -#define DRM_IOCTL_PVR_DEV_QUERY PVR_IOCTL(0x00, DRM_IOWR, dev_query) -#define DRM_IOCTL_PVR_CREATE_BO PVR_IOCTL(0x01, DRM_IOWR, create_bo) -#define DRM_IOCTL_PVR_GET_BO_MMAP_OFFSET \ - PVR_IOCTL(0x02, DRM_IOWR, get_bo_mmap_offset) -#define DRM_IOCTL_PVR_CREATE_VM_CONTEXT \ - PVR_IOCTL(0x03, DRM_IOWR, create_vm_context) -#define DRM_IOCTL_PVR_DESTROY_VM_CONTEXT \ - PVR_IOCTL(0x04, DRM_IOW, destroy_vm_context) -#define DRM_IOCTL_PVR_VM_MAP PVR_IOCTL(0x05, DRM_IOW, vm_map) -#define DRM_IOCTL_PVR_VM_UNMAP PVR_IOCTL(0x06, DRM_IOW, vm_unmap) -#define DRM_IOCTL_PVR_CREATE_CONTEXT PVR_IOCTL(0x07, DRM_IOWR, create_context) -#define DRM_IOCTL_PVR_DESTROY_CONTEXT PVR_IOCTL(0x08, DRM_IOW, destroy_context) -#define DRM_IOCTL_PVR_CREATE_FREE_LIST \ - PVR_IOCTL(0x09, DRM_IOWR, create_free_list) -#define DRM_IOCTL_PVR_DESTROY_FREE_LIST \ - PVR_IOCTL(0x0a, DRM_IOW, destroy_free_list) -#define DRM_IOCTL_PVR_CREATE_HWRT_DATASET \ - PVR_IOCTL(0x0b, DRM_IOWR, create_hwrt_dataset) -#define DRM_IOCTL_PVR_DESTROY_HWRT_DATASET \ - PVR_IOCTL(0x0c, DRM_IOW, destroy_hwrt_dataset) -#define DRM_IOCTL_PVR_SUBMIT_JOBS PVR_IOCTL(0x0d, DRM_IOW, submit_jobs) +#define PVR_IOCTL(_ioctl, _mode, _data) _mode(DRM_COMMAND_BASE + (_ioctl), struct drm_pvr_ioctl_##_data##_args) + +#define DRM_IOCTL_PVR_DEV_QUERY PVR_IOCTL(0x00, DRM_IOWR, dev_query) +#define DRM_IOCTL_PVR_CREATE_BO PVR_IOCTL(0x01, DRM_IOWR, create_bo) +#define DRM_IOCTL_PVR_GET_BO_MMAP_OFFSET PVR_IOCTL(0x02, DRM_IOWR, get_bo_mmap_offset) +#define DRM_IOCTL_PVR_CREATE_VM_CONTEXT PVR_IOCTL(0x03, DRM_IOWR, create_vm_context) +#define DRM_IOCTL_PVR_DESTROY_VM_CONTEXT PVR_IOCTL(0x04, DRM_IOW, destroy_vm_context) +#define DRM_IOCTL_PVR_VM_MAP PVR_IOCTL(0x05, DRM_IOW, vm_map) +#define DRM_IOCTL_PVR_VM_UNMAP PVR_IOCTL(0x06, DRM_IOW, vm_unmap) +#define DRM_IOCTL_PVR_CREATE_CONTEXT PVR_IOCTL(0x07, DRM_IOWR, create_context) +#define DRM_IOCTL_PVR_DESTROY_CONTEXT PVR_IOCTL(0x08, DRM_IOW, destroy_context) +#define DRM_IOCTL_PVR_CREATE_FREE_LIST PVR_IOCTL(0x09, DRM_IOWR, create_free_list) +#define DRM_IOCTL_PVR_DESTROY_FREE_LIST PVR_IOCTL(0x0a, DRM_IOW, destroy_free_list) +#define DRM_IOCTL_PVR_CREATE_HWRT_DATASET PVR_IOCTL(0x0b, DRM_IOWR, create_hwrt_dataset) +#define DRM_IOCTL_PVR_DESTROY_HWRT_DATASET PVR_IOCTL(0x0c, DRM_IOW, destroy_hwrt_dataset) +#define DRM_IOCTL_PVR_SUBMIT_JOBS PVR_IOCTL(0x0d, DRM_IOW, submit_jobs) /** * DOC: PowerVR IOCTL DEV_QUERY interface @@ -557,9 +546,8 @@ struct drm_pvr_ioctl_dev_query_args { #define DRM_PVR_BO_ALLOW_CPU_USERSPACE_ACCESS _BITULL(2) /* Bits 3..63 are reserved. */ -#define DRM_PVR_BO_FLAGS_MASK \ - (DRM_PVR_BO_BYPASS_DEVICE_CACHE | DRM_PVR_BO_PM_FW_PROTECT | \ - DRM_PVR_BO_ALLOW_CPU_USERSPACE_ACCESS) +#define DRM_PVR_BO_FLAGS_MASK \ + (DRM_PVR_BO_BYPASS_DEVICE_CACHE | DRM_PVR_BO_PM_FW_PROTECT | DRM_PVR_BO_ALLOW_CPU_USERSPACE_ACCESS) /** * struct drm_pvr_ioctl_create_bo_args - Arguments for %DRM_IOCTL_PVR_CREATE_BO @@ -1092,8 +1080,7 @@ struct drm_pvr_ioctl_destroy_hwrt_dataset_args { #define DRM_PVR_SYNC_OP_FLAG_SIGNAL _BITULL(31) #define DRM_PVR_SYNC_OP_FLAG_WAIT 0 -#define DRM_PVR_SYNC_OP_FLAGS_MASK \ - (DRM_PVR_SYNC_OP_FLAG_HANDLE_TYPE_MASK | DRM_PVR_SYNC_OP_FLAG_SIGNAL) +#define DRM_PVR_SYNC_OP_FLAGS_MASK (DRM_PVR_SYNC_OP_FLAG_HANDLE_TYPE_MASK | DRM_PVR_SYNC_OP_FLAG_SIGNAL) /** * struct drm_pvr_sync_op - Object describing a sync operation @@ -1133,9 +1120,7 @@ struct drm_pvr_sync_op { #define DRM_PVR_SUBMIT_JOB_GEOM_CMD_LAST _BITULL(1) #define DRM_PVR_SUBMIT_JOB_GEOM_CMD_SINGLE_CORE _BITULL(2) #define DRM_PVR_SUBMIT_JOB_GEOM_CMD_FLAGS_MASK \ - (DRM_PVR_SUBMIT_JOB_GEOM_CMD_FIRST | \ - DRM_PVR_SUBMIT_JOB_GEOM_CMD_LAST | \ - DRM_PVR_SUBMIT_JOB_GEOM_CMD_SINGLE_CORE) + (DRM_PVR_SUBMIT_JOB_GEOM_CMD_FIRST | DRM_PVR_SUBMIT_JOB_GEOM_CMD_LAST | DRM_PVR_SUBMIT_JOB_GEOM_CMD_SINGLE_CORE) /** * DOC: Flags for SUBMIT_JOB ioctl fragment command. @@ -1182,15 +1167,11 @@ struct drm_pvr_sync_op { #define DRM_PVR_SUBMIT_JOB_FRAG_CMD_GET_VIS_RESULTS _BITULL(5) #define DRM_PVR_SUBMIT_JOB_FRAG_CMD_PARTIAL_RENDER _BITULL(6) #define DRM_PVR_SUBMIT_JOB_FRAG_CMD_DISABLE_PIXELMERGE _BITULL(7) -#define DRM_PVR_SUBMIT_JOB_FRAG_CMD_FLAGS_MASK \ - (DRM_PVR_SUBMIT_JOB_FRAG_CMD_SINGLE_CORE | \ - DRM_PVR_SUBMIT_JOB_FRAG_CMD_DEPTHBUFFER | \ - DRM_PVR_SUBMIT_JOB_FRAG_CMD_STENCILBUFFER | \ - DRM_PVR_SUBMIT_JOB_FRAG_CMD_PREVENT_CDM_OVERLAP | \ - DRM_PVR_SUBMIT_JOB_FRAG_CMD_SCRATCHBUFFER | \ - DRM_PVR_SUBMIT_JOB_FRAG_CMD_GET_VIS_RESULTS | \ - DRM_PVR_SUBMIT_JOB_FRAG_CMD_PARTIAL_RENDER | \ - DRM_PVR_SUBMIT_JOB_FRAG_CMD_DISABLE_PIXELMERGE) +#define DRM_PVR_SUBMIT_JOB_FRAG_CMD_FLAGS_MASK \ + (DRM_PVR_SUBMIT_JOB_FRAG_CMD_SINGLE_CORE | DRM_PVR_SUBMIT_JOB_FRAG_CMD_DEPTHBUFFER | \ + DRM_PVR_SUBMIT_JOB_FRAG_CMD_STENCILBUFFER | DRM_PVR_SUBMIT_JOB_FRAG_CMD_PREVENT_CDM_OVERLAP | \ + DRM_PVR_SUBMIT_JOB_FRAG_CMD_SCRATCHBUFFER | DRM_PVR_SUBMIT_JOB_FRAG_CMD_GET_VIS_RESULTS | \ + DRM_PVR_SUBMIT_JOB_FRAG_CMD_PARTIAL_RENDER | DRM_PVR_SUBMIT_JOB_FRAG_CMD_DISABLE_PIXELMERGE) /** * DOC: Flags for SUBMIT_JOB ioctl compute command. @@ -1209,9 +1190,8 @@ struct drm_pvr_sync_op { */ #define DRM_PVR_SUBMIT_JOB_COMPUTE_CMD_PREVENT_ALL_OVERLAP _BITULL(0) #define DRM_PVR_SUBMIT_JOB_COMPUTE_CMD_SINGLE_CORE _BITULL(1) -#define DRM_PVR_SUBMIT_JOB_COMPUTE_CMD_FLAGS_MASK \ - (DRM_PVR_SUBMIT_JOB_COMPUTE_CMD_PREVENT_ALL_OVERLAP | \ - DRM_PVR_SUBMIT_JOB_COMPUTE_CMD_SINGLE_CORE) +#define DRM_PVR_SUBMIT_JOB_COMPUTE_CMD_FLAGS_MASK \ + (DRM_PVR_SUBMIT_JOB_COMPUTE_CMD_PREVENT_ALL_OVERLAP | DRM_PVR_SUBMIT_JOB_COMPUTE_CMD_SINGLE_CORE) /** * DOC: Flags for SUBMIT_JOB ioctl transfer command. @@ -1226,8 +1206,7 @@ struct drm_pvr_sync_op { */ #define DRM_PVR_SUBMIT_JOB_TRANSFER_CMD_SINGLE_CORE _BITULL(0) -#define DRM_PVR_SUBMIT_JOB_TRANSFER_CMD_FLAGS_MASK \ - DRM_PVR_SUBMIT_JOB_TRANSFER_CMD_SINGLE_CORE +#define DRM_PVR_SUBMIT_JOB_TRANSFER_CMD_FLAGS_MASK DRM_PVR_SUBMIT_JOB_TRANSFER_CMD_SINGLE_CORE /** * enum drm_pvr_job_type - Arguments for &struct drm_pvr_job.job_type diff --git a/include/arch/x86_64/drm/qaic_accel.h b/include/arch/x86_64/drm/qaic_accel.h index b6497637..491c646d 100644 --- a/include/arch/x86_64/drm/qaic_accel.h +++ b/include/arch/x86_64/drm/qaic_accel.h @@ -382,28 +382,15 @@ struct qaic_detach_slice { #define DRM_QAIC_PERF_STATS_BO 0x07 #define DRM_QAIC_DETACH_SLICE_BO 0x08 -#define DRM_IOCTL_QAIC_MANAGE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MANAGE, struct qaic_manage_msg) -#define DRM_IOCTL_QAIC_CREATE_BO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_CREATE_BO, struct qaic_create_bo) -#define DRM_IOCTL_QAIC_MMAP_BO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MMAP_BO, struct qaic_mmap_bo) -#define DRM_IOCTL_QAIC_ATTACH_SLICE_BO \ - DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_ATTACH_SLICE_BO, \ - struct qaic_attach_slice) -#define DRM_IOCTL_QAIC_EXECUTE_BO \ - DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_EXECUTE_BO, struct qaic_execute) -#define DRM_IOCTL_QAIC_PARTIAL_EXECUTE_BO \ - DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_PARTIAL_EXECUTE_BO, \ - struct qaic_execute) -#define DRM_IOCTL_QAIC_WAIT_BO \ - DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_WAIT_BO, struct qaic_wait) -#define DRM_IOCTL_QAIC_PERF_STATS_BO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_PERF_STATS_BO, \ - struct qaic_perf_stats) -#define DRM_IOCTL_QAIC_DETACH_SLICE_BO \ - DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_DETACH_SLICE_BO, \ - struct qaic_detach_slice) +#define DRM_IOCTL_QAIC_MANAGE DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MANAGE, struct qaic_manage_msg) +#define DRM_IOCTL_QAIC_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_CREATE_BO, struct qaic_create_bo) +#define DRM_IOCTL_QAIC_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MMAP_BO, struct qaic_mmap_bo) +#define DRM_IOCTL_QAIC_ATTACH_SLICE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_ATTACH_SLICE_BO, struct qaic_attach_slice) +#define DRM_IOCTL_QAIC_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_EXECUTE_BO, struct qaic_execute) +#define DRM_IOCTL_QAIC_PARTIAL_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_PARTIAL_EXECUTE_BO, struct qaic_execute) +#define DRM_IOCTL_QAIC_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_WAIT_BO, struct qaic_wait) +#define DRM_IOCTL_QAIC_PERF_STATS_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_PERF_STATS_BO, struct qaic_perf_stats) +#define DRM_IOCTL_QAIC_DETACH_SLICE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_DETACH_SLICE_BO, struct qaic_detach_slice) #if defined(__cplusplus) } diff --git a/include/arch/x86_64/drm/qxl_drm.h b/include/arch/x86_64/drm/qxl_drm.h index 56bed67c..9368e139 100644 --- a/include/arch/x86_64/drm/qxl_drm.h +++ b/include/arch/x86_64/drm/qxl_drm.h @@ -125,29 +125,19 @@ struct drm_qxl_alloc_surf { __u32 pad; }; -#define DRM_IOCTL_QXL_ALLOC \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC, struct drm_qxl_alloc) +#define DRM_IOCTL_QXL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC, struct drm_qxl_alloc) -#define DRM_IOCTL_QXL_MAP \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_MAP, struct drm_qxl_map) +#define DRM_IOCTL_QXL_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_MAP, struct drm_qxl_map) -#define DRM_IOCTL_QXL_EXECBUFFER \ - DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_EXECBUFFER, \ - struct drm_qxl_execbuffer) +#define DRM_IOCTL_QXL_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_EXECBUFFER, struct drm_qxl_execbuffer) -#define DRM_IOCTL_QXL_UPDATE_AREA \ - DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_UPDATE_AREA, \ - struct drm_qxl_update_area) +#define DRM_IOCTL_QXL_UPDATE_AREA DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_UPDATE_AREA, struct drm_qxl_update_area) -#define DRM_IOCTL_QXL_GETPARAM \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_GETPARAM, struct drm_qxl_getparam) +#define DRM_IOCTL_QXL_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_GETPARAM, struct drm_qxl_getparam) -#define DRM_IOCTL_QXL_CLIENTCAP \ - DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_CLIENTCAP, struct drm_qxl_clientcap) +#define DRM_IOCTL_QXL_CLIENTCAP DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_CLIENTCAP, struct drm_qxl_clientcap) -#define DRM_IOCTL_QXL_ALLOC_SURF \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC_SURF, \ - struct drm_qxl_alloc_surf) +#define DRM_IOCTL_QXL_ALLOC_SURF DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC_SURF, struct drm_qxl_alloc_surf) #if defined(__cplusplus) } diff --git a/include/arch/x86_64/drm/radeon_drm.h b/include/arch/x86_64/drm/radeon_drm.h index 6ac625ab..663e20f9 100644 --- a/include/arch/x86_64/drm/radeon_drm.h +++ b/include/arch/x86_64/drm/radeon_drm.h @@ -454,8 +454,7 @@ typedef struct { unsigned int last_dispatch; unsigned int last_clear; - struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS] - [RADEON_NR_TEX_REGIONS + 1]; + struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 1]; unsigned int tex_age[RADEON_NR_TEX_HEAPS]; int ctx_owner; int pfState; /* number of 3d windows (0,1,2ormore) */ @@ -518,100 +517,53 @@ typedef struct { #define DRM_RADEON_GEM_OP 0x2c #define DRM_RADEON_GEM_USERPTR 0x2d -#define DRM_IOCTL_RADEON_CP_INIT \ - DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) -#define DRM_IOCTL_RADEON_CP_START DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_START) -#define DRM_IOCTL_RADEON_CP_STOP \ - DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) -#define DRM_IOCTL_RADEON_CP_RESET DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) -#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) -#define DRM_IOCTL_RADEON_RESET DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_RESET) -#define DRM_IOCTL_RADEON_FULLSCREEN \ - DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, \ - drm_radeon_fullscreen_t) -#define DRM_IOCTL_RADEON_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_SWAP) -#define DRM_IOCTL_RADEON_CLEAR \ - DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) -#define DRM_IOCTL_RADEON_VERTEX \ - DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) -#define DRM_IOCTL_RADEON_INDICES \ - DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) -#define DRM_IOCTL_RADEON_STIPPLE \ - DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) -#define DRM_IOCTL_RADEON_INDIRECT \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) -#define DRM_IOCTL_RADEON_TEXTURE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) -#define DRM_IOCTL_RADEON_VERTEX2 \ - DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) -#define DRM_IOCTL_RADEON_CMDBUF \ - DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) -#define DRM_IOCTL_RADEON_GETPARAM \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) -#define DRM_IOCTL_RADEON_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_FLIP) -#define DRM_IOCTL_RADEON_ALLOC \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) -#define DRM_IOCTL_RADEON_FREE \ - DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) -#define DRM_IOCTL_RADEON_INIT_HEAP \ - DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, \ - drm_radeon_mem_init_heap_t) -#define DRM_IOCTL_RADEON_IRQ_EMIT \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) -#define DRM_IOCTL_RADEON_IRQ_WAIT \ - DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) -#define DRM_IOCTL_RADEON_CP_RESUME \ - DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) -#define DRM_IOCTL_RADEON_SETPARAM \ - DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) -#define DRM_IOCTL_RADEON_SURF_ALLOC \ - DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, \ - drm_radeon_surface_alloc_t) -#define DRM_IOCTL_RADEON_SURF_FREE \ - DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, \ - drm_radeon_surface_free_t) +#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) +#define DRM_IOCTL_RADEON_CP_START DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_START) +#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) +#define DRM_IOCTL_RADEON_CP_RESET DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) +#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) +#define DRM_IOCTL_RADEON_RESET DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_RESET) +#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) +#define DRM_IOCTL_RADEON_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_SWAP) +#define DRM_IOCTL_RADEON_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) +#define DRM_IOCTL_RADEON_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) +#define DRM_IOCTL_RADEON_INDICES DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) +#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) +#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) +#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) +#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) +#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) +#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) +#define DRM_IOCTL_RADEON_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_FLIP) +#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) +#define DRM_IOCTL_RADEON_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) +#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) +#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) +#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) +#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) +#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) +#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) +#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) /* KMS */ -#define DRM_IOCTL_RADEON_GEM_INFO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, \ - struct drm_radeon_gem_info) -#define DRM_IOCTL_RADEON_GEM_CREATE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, \ - struct drm_radeon_gem_create) -#define DRM_IOCTL_RADEON_GEM_MMAP \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, \ - struct drm_radeon_gem_mmap) -#define DRM_IOCTL_RADEON_GEM_PREAD \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, \ - struct drm_radeon_gem_pread) -#define DRM_IOCTL_RADEON_GEM_PWRITE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, \ - struct drm_radeon_gem_pwrite) -#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, \ - struct drm_radeon_gem_set_domain) -#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE \ - DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, \ - struct drm_radeon_gem_wait_idle) -#define DRM_IOCTL_RADEON_CS \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) -#define DRM_IOCTL_RADEON_INFO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) -#define DRM_IOCTL_RADEON_GEM_SET_TILING \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, \ - struct drm_radeon_gem_set_tiling) -#define DRM_IOCTL_RADEON_GEM_GET_TILING \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, \ - struct drm_radeon_gem_get_tiling) -#define DRM_IOCTL_RADEON_GEM_BUSY \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, \ - struct drm_radeon_gem_busy) -#define DRM_IOCTL_RADEON_GEM_VA \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va) -#define DRM_IOCTL_RADEON_GEM_OP \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op) -#define DRM_IOCTL_RADEON_GEM_USERPTR \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, \ - struct drm_radeon_gem_userptr) +#define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info) +#define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create) +#define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap) +#define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) +#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite) +#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) +#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE \ + DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle) +#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) +#define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) +#define DRM_IOCTL_RADEON_GEM_SET_TILING \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) +#define DRM_IOCTL_RADEON_GEM_GET_TILING \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) +#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) +#define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va) +#define DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op) +#define DRM_IOCTL_RADEON_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr) typedef struct drm_radeon_init { enum { @@ -648,10 +600,7 @@ typedef struct drm_radeon_cp_stop { } drm_radeon_cp_stop_t; typedef struct drm_radeon_fullscreen { - enum { - RADEON_INIT_FULLSCREEN = 0x01, - RADEON_CLEANUP_FULLSCREEN = 0x02 - } func; + enum { RADEON_INIT_FULLSCREEN = 0x01, RADEON_CLEANUP_FULLSCREEN = 0x02 } func; } drm_radeon_fullscreen_t; #define CLEAR_X1 0 @@ -1006,8 +955,7 @@ struct drm_radeon_gem_va { /* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */ #define RADEON_CS_KEEP_TILING_FLAGS 0x01 #define RADEON_CS_USE_VM 0x02 -#define RADEON_CS_END_OF_FRAME \ - 0x04 /* a hint from userspace which CS is the last one */ +#define RADEON_CS_END_OF_FRAME 0x04 /* a hint from userspace which CS is the last one */ /* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */ #define RADEON_CS_RING_GFX 0 @@ -1055,13 +1003,12 @@ struct drm_radeon_cs { #define RADEON_INFO_WANT_HYPERZ 0x07 #define RADEON_INFO_WANT_CMASK 0x08 /* get access to CMASK on r300 */ #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */ -#define RADEON_INFO_NUM_BACKENDS \ - 0x0a /* DB/backends for r600+ - need for OQ \ - */ -#define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */ -#define RADEON_INFO_FUSION_GART_WORKING \ - 0x0c /* fusion writes to GTT were broken before this */ -#define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map, needed by mesa */ +#define RADEON_INFO_NUM_BACKENDS \ + 0x0a /* DB/backends for r600+ - need for OQ \ + */ +#define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */ +#define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */ +#define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map, needed by mesa */ /* virtual address start, va < start are reserved by the kernel */ #define RADEON_INFO_VA_START 0x0e /* maximum size of ib using the virtual memory cs */ diff --git a/include/arch/x86_64/drm/tegra_drm.h b/include/arch/x86_64/drm/tegra_drm.h index 2219bf94..7532fd6f 100644 --- a/include/arch/x86_64/drm/tegra_drm.h +++ b/include/arch/x86_64/drm/tegra_drm.h @@ -642,47 +642,26 @@ struct drm_tegra_gem_get_flags { #define DRM_TEGRA_GEM_SET_FLAGS 0x0c #define DRM_TEGRA_GEM_GET_FLAGS 0x0d -#define DRM_IOCTL_TEGRA_GEM_CREATE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, \ - struct drm_tegra_gem_create) -#define DRM_IOCTL_TEGRA_GEM_MMAP \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, \ - struct drm_tegra_gem_mmap) -#define DRM_IOCTL_TEGRA_SYNCPT_READ \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, \ - struct drm_tegra_syncpt_read) -#define DRM_IOCTL_TEGRA_SYNCPT_INCR \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, \ - struct drm_tegra_syncpt_incr) -#define DRM_IOCTL_TEGRA_SYNCPT_WAIT \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, \ - struct drm_tegra_syncpt_wait) -#define DRM_IOCTL_TEGRA_OPEN_CHANNEL \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, \ - struct drm_tegra_open_channel) -#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, \ - struct drm_tegra_close_channel) -#define DRM_IOCTL_TEGRA_GET_SYNCPT \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, \ - struct drm_tegra_get_syncpt) -#define DRM_IOCTL_TEGRA_SUBMIT \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit) -#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, \ - struct drm_tegra_get_syncpt_base) -#define DRM_IOCTL_TEGRA_GEM_SET_TILING \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, \ - struct drm_tegra_gem_set_tiling) -#define DRM_IOCTL_TEGRA_GEM_GET_TILING \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, \ - struct drm_tegra_gem_get_tiling) -#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, \ - struct drm_tegra_gem_set_flags) -#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, \ - struct drm_tegra_gem_get_flags) +#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create) +#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap) +#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read) +#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr) +#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait) +#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel) +#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_close_channel) +#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt) +#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit) +#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base) +#define DRM_IOCTL_TEGRA_GEM_SET_TILING \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling) +#define DRM_IOCTL_TEGRA_GEM_GET_TILING \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling) +#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags) +#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags) /* New Tegra DRM UAPI */ @@ -750,10 +729,9 @@ struct drm_tegra_channel_close { * DRM_TEGRA_CHANNEL_MAP_READ: create mapping that allows HW read access * DRM_TEGRA_CHANNEL_MAP_WRITE: create mapping that allows HW write access */ -#define DRM_TEGRA_CHANNEL_MAP_READ (1 << 0) -#define DRM_TEGRA_CHANNEL_MAP_WRITE (1 << 1) -#define DRM_TEGRA_CHANNEL_MAP_READ_WRITE \ - (DRM_TEGRA_CHANNEL_MAP_READ | DRM_TEGRA_CHANNEL_MAP_WRITE) +#define DRM_TEGRA_CHANNEL_MAP_READ (1 << 0) +#define DRM_TEGRA_CHANNEL_MAP_WRITE (1 << 1) +#define DRM_TEGRA_CHANNEL_MAP_READ_WRITE (DRM_TEGRA_CHANNEL_MAP_READ | DRM_TEGRA_CHANNEL_MAP_WRITE) struct drm_tegra_channel_map { /** @@ -1070,23 +1048,15 @@ struct drm_tegra_syncpoint_wait { __u32 padding; }; -#define DRM_IOCTL_TEGRA_CHANNEL_OPEN \ - DRM_IOWR(DRM_COMMAND_BASE + 0x10, struct drm_tegra_channel_open) -#define DRM_IOCTL_TEGRA_CHANNEL_CLOSE \ - DRM_IOWR(DRM_COMMAND_BASE + 0x11, struct drm_tegra_channel_close) -#define DRM_IOCTL_TEGRA_CHANNEL_MAP \ - DRM_IOWR(DRM_COMMAND_BASE + 0x12, struct drm_tegra_channel_map) -#define DRM_IOCTL_TEGRA_CHANNEL_UNMAP \ - DRM_IOWR(DRM_COMMAND_BASE + 0x13, struct drm_tegra_channel_unmap) -#define DRM_IOCTL_TEGRA_CHANNEL_SUBMIT \ - DRM_IOWR(DRM_COMMAND_BASE + 0x14, struct drm_tegra_channel_submit) - -#define DRM_IOCTL_TEGRA_SYNCPOINT_ALLOCATE \ - DRM_IOWR(DRM_COMMAND_BASE + 0x20, struct drm_tegra_syncpoint_allocate) -#define DRM_IOCTL_TEGRA_SYNCPOINT_FREE \ - DRM_IOWR(DRM_COMMAND_BASE + 0x21, struct drm_tegra_syncpoint_free) -#define DRM_IOCTL_TEGRA_SYNCPOINT_WAIT \ - DRM_IOWR(DRM_COMMAND_BASE + 0x22, struct drm_tegra_syncpoint_wait) +#define DRM_IOCTL_TEGRA_CHANNEL_OPEN DRM_IOWR(DRM_COMMAND_BASE + 0x10, struct drm_tegra_channel_open) +#define DRM_IOCTL_TEGRA_CHANNEL_CLOSE DRM_IOWR(DRM_COMMAND_BASE + 0x11, struct drm_tegra_channel_close) +#define DRM_IOCTL_TEGRA_CHANNEL_MAP DRM_IOWR(DRM_COMMAND_BASE + 0x12, struct drm_tegra_channel_map) +#define DRM_IOCTL_TEGRA_CHANNEL_UNMAP DRM_IOWR(DRM_COMMAND_BASE + 0x13, struct drm_tegra_channel_unmap) +#define DRM_IOCTL_TEGRA_CHANNEL_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + 0x14, struct drm_tegra_channel_submit) + +#define DRM_IOCTL_TEGRA_SYNCPOINT_ALLOCATE DRM_IOWR(DRM_COMMAND_BASE + 0x20, struct drm_tegra_syncpoint_allocate) +#define DRM_IOCTL_TEGRA_SYNCPOINT_FREE DRM_IOWR(DRM_COMMAND_BASE + 0x21, struct drm_tegra_syncpoint_free) +#define DRM_IOCTL_TEGRA_SYNCPOINT_WAIT DRM_IOWR(DRM_COMMAND_BASE + 0x22, struct drm_tegra_syncpoint_wait) #if defined(__cplusplus) } diff --git a/include/arch/x86_64/drm/v3d_drm.h b/include/arch/x86_64/drm/v3d_drm.h index 1ae21341..f4f75a1d 100644 --- a/include/arch/x86_64/drm/v3d_drm.h +++ b/include/arch/x86_64/drm/v3d_drm.h @@ -45,43 +45,24 @@ extern "C" { #define DRM_V3D_PERFMON_GET_COUNTER 0x0c #define DRM_V3D_PERFMON_SET_GLOBAL 0x0d -#define DRM_IOCTL_V3D_SUBMIT_CL \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl) -#define DRM_IOCTL_V3D_WAIT_BO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo) -#define DRM_IOCTL_V3D_CREATE_BO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo) -#define DRM_IOCTL_V3D_MMAP_BO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo) -#define DRM_IOCTL_V3D_GET_PARAM \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param) -#define DRM_IOCTL_V3D_GET_BO_OFFSET \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, \ - struct drm_v3d_get_bo_offset) -#define DRM_IOCTL_V3D_SUBMIT_TFU \ - DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, \ - struct drm_v3d_submit_tfu) -#define DRM_IOCTL_V3D_SUBMIT_CSD \ - DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, \ - struct drm_v3d_submit_csd) -#define DRM_IOCTL_V3D_PERFMON_CREATE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_CREATE, \ - struct drm_v3d_perfmon_create) -#define DRM_IOCTL_V3D_PERFMON_DESTROY \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_DESTROY, \ - struct drm_v3d_perfmon_destroy) -#define DRM_IOCTL_V3D_PERFMON_GET_VALUES \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_VALUES, \ - struct drm_v3d_perfmon_get_values) -#define DRM_IOCTL_V3D_SUBMIT_CPU \ - DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CPU, \ - struct drm_v3d_submit_cpu) -#define DRM_IOCTL_V3D_PERFMON_GET_COUNTER \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_COUNTER, \ - struct drm_v3d_perfmon_get_counter) -#define DRM_IOCTL_V3D_PERFMON_SET_GLOBAL \ - DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_PERFMON_SET_GLOBAL, \ - struct drm_v3d_perfmon_set_global) +#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl) +#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo) +#define DRM_IOCTL_V3D_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo) +#define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo) +#define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param) +#define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset) +#define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu) +#define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd) +#define DRM_IOCTL_V3D_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_CREATE, struct drm_v3d_perfmon_create) +#define DRM_IOCTL_V3D_PERFMON_DESTROY \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_DESTROY, struct drm_v3d_perfmon_destroy) +#define DRM_IOCTL_V3D_PERFMON_GET_VALUES \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_VALUES, struct drm_v3d_perfmon_get_values) +#define DRM_IOCTL_V3D_SUBMIT_CPU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CPU, struct drm_v3d_submit_cpu) +#define DRM_IOCTL_V3D_PERFMON_GET_COUNTER \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_COUNTER, struct drm_v3d_perfmon_get_counter) +#define DRM_IOCTL_V3D_PERFMON_SET_GLOBAL \ + DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_PERFMON_SET_GLOBAL, struct drm_v3d_perfmon_set_global) #define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01 #define DRM_V3D_SUBMIT_EXTENSION 0x02 diff --git a/include/arch/x86_64/drm/vc4_drm.h b/include/arch/x86_64/drm/vc4_drm.h index 691fa998..6ce70979 100644 --- a/include/arch/x86_64/drm/vc4_drm.h +++ b/include/arch/x86_64/drm/vc4_drm.h @@ -46,45 +46,24 @@ extern "C" { #define DRM_VC4_PERFMON_DESTROY 0x0d #define DRM_VC4_PERFMON_GET_VALUES 0x0e -#define DRM_IOCTL_VC4_SUBMIT_CL \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) -#define DRM_IOCTL_VC4_WAIT_SEQNO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, \ - struct drm_vc4_wait_seqno) -#define DRM_IOCTL_VC4_WAIT_BO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo) -#define DRM_IOCTL_VC4_CREATE_BO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) -#define DRM_IOCTL_VC4_MMAP_BO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) -#define DRM_IOCTL_VC4_CREATE_SHADER_BO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, \ - struct drm_vc4_create_shader_bo) -#define DRM_IOCTL_VC4_GET_HANG_STATE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, \ - struct drm_vc4_get_hang_state) -#define DRM_IOCTL_VC4_GET_PARAM \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param) -#define DRM_IOCTL_VC4_SET_TILING \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, \ - struct drm_vc4_set_tiling) -#define DRM_IOCTL_VC4_GET_TILING \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, \ - struct drm_vc4_get_tiling) -#define DRM_IOCTL_VC4_LABEL_BO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo) -#define DRM_IOCTL_VC4_GEM_MADVISE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, \ - struct drm_vc4_gem_madvise) -#define DRM_IOCTL_VC4_PERFMON_CREATE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_CREATE, \ - struct drm_vc4_perfmon_create) -#define DRM_IOCTL_VC4_PERFMON_DESTROY \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_DESTROY, \ - struct drm_vc4_perfmon_destroy) -#define DRM_IOCTL_VC4_PERFMON_GET_VALUES \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_GET_VALUES, \ - struct drm_vc4_perfmon_get_values) +#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) +#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) +#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo) +#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) +#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) +#define DRM_IOCTL_VC4_CREATE_SHADER_BO \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) +#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) +#define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param) +#define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling) +#define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling) +#define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo) +#define DRM_IOCTL_VC4_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise) +#define DRM_IOCTL_VC4_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_CREATE, struct drm_vc4_perfmon_create) +#define DRM_IOCTL_VC4_PERFMON_DESTROY \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_DESTROY, struct drm_vc4_perfmon_destroy) +#define DRM_IOCTL_VC4_PERFMON_GET_VALUES \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_GET_VALUES, struct drm_vc4_perfmon_get_values) struct drm_vc4_submit_rcl_surface { __u32 hindex; /* Handle index, or ~0 if not present. */ diff --git a/include/arch/x86_64/drm/vgem_drm.h b/include/arch/x86_64/drm/vgem_drm.h index b2d8eed6..9e68e0da 100644 --- a/include/arch/x86_64/drm/vgem_drm.h +++ b/include/arch/x86_64/drm/vgem_drm.h @@ -39,12 +39,8 @@ extern "C" { #define DRM_VGEM_FENCE_ATTACH 0x1 #define DRM_VGEM_FENCE_SIGNAL 0x2 -#define DRM_IOCTL_VGEM_FENCE_ATTACH \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VGEM_FENCE_ATTACH, \ - struct drm_vgem_fence_attach) -#define DRM_IOCTL_VGEM_FENCE_SIGNAL \ - DRM_IOW(DRM_COMMAND_BASE + DRM_VGEM_FENCE_SIGNAL, \ - struct drm_vgem_fence_signal) +#define DRM_IOCTL_VGEM_FENCE_ATTACH DRM_IOWR(DRM_COMMAND_BASE + DRM_VGEM_FENCE_ATTACH, struct drm_vgem_fence_attach) +#define DRM_IOCTL_VGEM_FENCE_SIGNAL DRM_IOW(DRM_COMMAND_BASE + DRM_VGEM_FENCE_SIGNAL, struct drm_vgem_fence_signal) struct drm_vgem_fence_attach { __u32 handle; diff --git a/include/arch/x86_64/drm/virtgpu_drm.h b/include/arch/x86_64/drm/virtgpu_drm.h index 77b8c034..77ce25d7 100644 --- a/include/arch/x86_64/drm/virtgpu_drm.h +++ b/include/arch/x86_64/drm/virtgpu_drm.h @@ -52,9 +52,8 @@ extern "C" { #define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01 #define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02 #define VIRTGPU_EXECBUF_RING_IDX 0x04 -#define VIRTGPU_EXECBUF_FLAGS \ - (VIRTGPU_EXECBUF_FENCE_FD_IN | VIRTGPU_EXECBUF_FENCE_FD_OUT | \ - VIRTGPU_EXECBUF_RING_IDX | 0) +#define VIRTGPU_EXECBUF_FLAGS \ + (VIRTGPU_EXECBUF_FENCE_FD_IN | VIRTGPU_EXECBUF_FENCE_FD_OUT | VIRTGPU_EXECBUF_RING_IDX | 0) struct drm_virtgpu_map { __u64 offset; /* use for mmap system call */ @@ -78,9 +77,9 @@ struct drm_virtgpu_execbuffer { __u64 command; /* void* */ __u64 bo_handles; __u32 num_bo_handles; - __s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) - */ - __u32 ring_idx; /* command ring index (see VIRTGPU_EXECBUF_RING_IDX) */ + __s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) + */ + __u32 ring_idx; /* command ring index (see VIRTGPU_EXECBUF_RING_IDX) */ __u32 syncobj_stride; /* size of @drm_virtgpu_execbuffer_syncobj */ __u32 num_in_syncobjs; __u32 num_out_syncobjs; @@ -92,14 +91,12 @@ struct drm_virtgpu_execbuffer { #define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */ #define VIRTGPU_PARAM_RESOURCE_BLOB 3 /* DRM_VIRTGPU_RESOURCE_CREATE_BLOB */ #define VIRTGPU_PARAM_HOST_VISIBLE 4 /* Host blob resources are mappable */ -#define VIRTGPU_PARAM_CROSS_DEVICE \ - 5 /* Cross virtio-device resource sharing \ - */ -#define VIRTGPU_PARAM_CONTEXT_INIT 6 /* DRM_VIRTGPU_CONTEXT_INIT */ -#define VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs \ - 7 /* Bitmask of supported capability set ids */ -#define VIRTGPU_PARAM_EXPLICIT_DEBUG_NAME \ - 8 /* Ability to set debug name from userspace */ +#define VIRTGPU_PARAM_CROSS_DEVICE \ + 5 /* Cross virtio-device resource sharing \ + */ +#define VIRTGPU_PARAM_CONTEXT_INIT 6 /* DRM_VIRTGPU_CONTEXT_INIT */ +#define VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs 7 /* Bitmask of supported capability set ids */ +#define VIRTGPU_PARAM_EXPLICIT_DEBUG_NAME 8 /* Ability to set debug name from userspace */ struct drm_virtgpu_getparam { __u64 param; @@ -119,8 +116,8 @@ struct drm_virtgpu_resource_create { __u32 last_level; __u32 nr_samples; __u32 flags; - __u32 bo_handle; /* if this is set - recreate a new resource attached to - this bo ? */ + __u32 bo_handle; /* if this is set - recreate a new resource attached to + this bo ? */ __u32 res_handle; /* returned by kernel */ __u32 size; /* validate transfer in the host */ __u32 stride; /* validate transfer in the host */ @@ -229,48 +226,33 @@ struct drm_virtgpu_context_init { */ #define VIRTGPU_EVENT_FENCE_SIGNALED 0x90000000 -#define DRM_IOCTL_VIRTGPU_MAP \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map) +#define DRM_IOCTL_VIRTGPU_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map) -#define DRM_IOCTL_VIRTGPU_EXECBUFFER \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER, \ - struct drm_virtgpu_execbuffer) +#define DRM_IOCTL_VIRTGPU_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER, struct drm_virtgpu_execbuffer) -#define DRM_IOCTL_VIRTGPU_GETPARAM \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM, \ - struct drm_virtgpu_getparam) +#define DRM_IOCTL_VIRTGPU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM, struct drm_virtgpu_getparam) -#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, \ - struct drm_virtgpu_resource_create) +#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, struct drm_virtgpu_resource_create) -#define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \ - struct drm_virtgpu_resource_info) +#define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, struct drm_virtgpu_resource_info) -#define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, \ - struct drm_virtgpu_3d_transfer_from_host) +#define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, struct drm_virtgpu_3d_transfer_from_host) -#define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, \ - struct drm_virtgpu_3d_transfer_to_host) +#define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, struct drm_virtgpu_3d_transfer_to_host) -#define DRM_IOCTL_VIRTGPU_WAIT \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, \ - struct drm_virtgpu_3d_wait) +#define DRM_IOCTL_VIRTGPU_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, struct drm_virtgpu_3d_wait) -#define DRM_IOCTL_VIRTGPU_GET_CAPS \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \ - struct drm_virtgpu_get_caps) +#define DRM_IOCTL_VIRTGPU_GET_CAPS DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, struct drm_virtgpu_get_caps) -#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB, \ - struct drm_virtgpu_resource_create_blob) +#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB, struct drm_virtgpu_resource_create_blob) -#define DRM_IOCTL_VIRTGPU_CONTEXT_INIT \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT, \ - struct drm_virtgpu_context_init) +#define DRM_IOCTL_VIRTGPU_CONTEXT_INIT \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT, struct drm_virtgpu_context_init) #if defined(__cplusplus) } diff --git a/include/arch/x86_64/drm/vmwgfx_drm.h b/include/arch/x86_64/drm/vmwgfx_drm.h index 1103ccfd..abb0d219 100644 --- a/include/arch/x86_64/drm/vmwgfx_drm.h +++ b/include/arch/x86_64/drm/vmwgfx_drm.h @@ -123,10 +123,7 @@ extern "C" { * enum drm_vmw_handle_type - handle type for ref ioctls * */ -enum drm_vmw_handle_type { - DRM_VMW_HANDLE_LEGACY = 0, - DRM_VMW_HANDLE_PRIME = 1 -}; +enum drm_vmw_handle_type { DRM_VMW_HANDLE_LEGACY = 0, DRM_VMW_HANDLE_PRIME = 1 }; /** * struct drm_vmw_getparam_arg diff --git a/include/arch/x86_64/drm/xe_drm.h b/include/arch/x86_64/drm/xe_drm.h index e170d120..9a3efa5c 100644 --- a/include/arch/x86_64/drm/xe_drm.h +++ b/include/arch/x86_64/drm/xe_drm.h @@ -105,37 +105,21 @@ extern "C" { /* Must be kept compact -- no holes */ -#define DRM_IOCTL_XE_DEVICE_QUERY \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, \ - struct drm_xe_device_query) -#define DRM_IOCTL_XE_GEM_CREATE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create) -#define DRM_IOCTL_XE_GEM_MMAP_OFFSET \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, \ - struct drm_xe_gem_mmap_offset) -#define DRM_IOCTL_XE_VM_CREATE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create) -#define DRM_IOCTL_XE_VM_DESTROY \ - DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy) -#define DRM_IOCTL_XE_VM_BIND \ - DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind) -#define DRM_IOCTL_XE_EXEC_QUEUE_CREATE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, \ - struct drm_xe_exec_queue_create) -#define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY \ - DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, \ - struct drm_xe_exec_queue_destroy) -#define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, \ - struct drm_xe_exec_queue_get_property) -#define DRM_IOCTL_XE_EXEC \ - DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec) -#define DRM_IOCTL_XE_WAIT_USER_FENCE \ - DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, \ - struct drm_xe_wait_user_fence) -#define DRM_IOCTL_XE_OBSERVATION \ - DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OBSERVATION, \ - struct drm_xe_observation_param) +#define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query) +#define DRM_IOCTL_XE_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create) +#define DRM_IOCTL_XE_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset) +#define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create) +#define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy) +#define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind) +#define DRM_IOCTL_XE_EXEC_QUEUE_CREATE \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create) +#define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY \ + DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy) +#define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property) +#define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec) +#define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence) +#define DRM_IOCTL_XE_OBSERVATION DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OBSERVATION, struct drm_xe_observation_param) /** * DOC: Xe IOCTL Extensions |